[读书笔记]Design Rules in a Semiconductor Foundry (Eitan N. Shauly)

2025/11/17~11/27

1.Layout Design Rules

2.Front-End-of-Line Topological Design Rules

 AA, WELL, GUARD RING, VT, DGO, POLY, N/PSD 

3.Back-End-of-Line Topological Design Rules

   (1) cont, metal, via

   (2) EM，slot（slot insert）

   (3) middle-of-line (MOL)

cont加入Ti和TiN作为粘合剂，改善钨填充质量，减小cont接触电阻。

4. Coverage Rules and Insertion Utilities (平坦化)

（1）density对cmp的影响：

（2）Dummy Fill Methods

       1.rule-based

       2.model-based

      3.Net-Aware and Timing-Aware DM Fill

          larger space + 禁止上下层金属填充

       4.cell fill

       5.dummy effct:

          c,r,i

          散热

      6.slot

5.Design Rules, Guidelines, and Modeling for Analog Modules

(1). RF device：speed,isolation

(2). HV FET

(3) high-frequency  BJT:SiGe

(4) R,C:

    guideline(recommend)for better performances

6.Stress-Related Layout Design Rules and Modeling

  (1) piezoresistance effect,压阻效应

应力源：substrate crystallographic orientation

              STI: LOD (length of diffusion) and OSE (oxide space effect)

              SMT (stress memorization technique), cESL (contact etch stop layer) and eSiGe (embedded SiGe).

  (2)晶向影响迁移率

  （3）STI: LOD,OSE

应力主要源于STI氧化物与硅衬底之间的热膨胀不同

改善：加dummy

 （4）cESL,eSiGe(S/D)

8.Planar CMOS Process Flow for Digital, Mixed-Signal, and RFCMOS Applications

  (1)节点缩小，功耗和漏电问题

      mix_thin/thick gate oxide

  (2)RMG(replacement metal gate)

         28,20nm

  (3) buck,epi,AA,well,gate,

9.Reliability Driven Design Rule

  (1)FEOL foundry qualification test

     TDDB, GOI, HCI ,NBTI (negative bias temperature instability)

  (2)BEOL foundry qualification tests

      EM (electromigration), SM (stress migration) and TDDB (inter-metal dielectric TDDB)

  (3)MIM

      TDDB,VBD

  (4)Automotive Qualification

      design rule

      funticon safety