Xilinx_FPGA_SOC ERROR1 解决

最新推荐文章于 2025-10-20 21:38:20 发布

原创最新推荐文章于 2025-10-20 21:38:20 发布 · 2.7k 阅读

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本文介绍了解决特定EDA工具中出现的逻辑块无法解析错误的方法。通过删除相关目录、创建新的综合与实现运行并调整设置等步骤，有效地解决了该问题。

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ERROR:

[NgdBuild 604] logical block 'system_i/chipscope_axi_monitor_0/chipscope_axi_monitor_0/U_ILA' with type 'chipscope_axi_monitor_0' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'chipscope_axi_monitor_0' is not supported in target 'zynq'.

解决方案：

1. Removed directory <PROJECT_NAME>.src/sources_1/edk/<EMBEDDED_NAME>/implementation
2. Removed directory <PROJECT_NAME>.src/sources_1/edk/<EMBEDDED_NAME>/synthesis
3. Created new synthesis and implementation runs.
4. Set the new runs as "active".
5. Removed old runs.
6. Opened XPS by double-clicking in the embedded design under the sources tab.
7. Closed XPS without doing anything.
8. Selected the new synthesis run and clicked on "Reset Selected Runs".
9. Selected the new implementation run and clicked on "Launch Selected Runs".