HDLBits Examsece241 2014 q5a

最新推荐文章于 2024-11-12 14:43:43 发布

原创

最新推荐文章于 2024-11-12 14:43:43 发布 · 1.4k 阅读

标签

#verilog #fpga开发

收录于

这篇文章介绍了如何使用Moore状态机设计一个处理任意长度输入的2's complement转换器，包括状态机的三个阶段划分、补码规则应用和关键代码实现。当输入全0时处理正数，输入出现1后进行负数转换，最终通过异步复位控制转换过程。

HDLBits Exams/ece241 2014 q5a

1.题目

题目链接：https://hdlbits.01xz.net/wiki/Exams/ece241_2014_q5a

You are to design a one-input one-output serial 2’s complementer Moore state machine. The input (x) is a series of bits (one per clock cycle) beginning with the least-significant bit of the number, and the output (Z) is the 2’s complement of the input. The machine will accept input numbers of arbitrary length. The circuit requires an asynchronous reset. The conversion begins when Reset is released and stops when Reset is asserted.

题目大意为用Moore状态机输出二进制数据的补码。