四、Sequential Logic
Finite State Machines
1、Simple FSM 1(asynchronous reset)
Problem Statement：
This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.
module top_module(
input clk,
input areset,
input in,
output out
);
parameter A=0, B=1;
reg state, next_state;
always @(posedge clk or posedge areset) begin
if(areset)
state <= B;
else
state <= next_state;
end
always @(*) begin
if(areset)
next_state <= B;
else
case(state)
A :
if(in)
next_state <= A;
else
next_state <= B;
B :
if(in)
next_state <= B;
else
next_state <= A;
default : ;
endcase
end
assign out = (state) ? 1'b1 : 1'b0;
endmodule2、Simple FSM 1(synchronous reset)
Problem Statement：
This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.
module top_module(clk, reset, in, out);
input clk;
input reset;
input in;
output out;
reg out;
parameter A=0,B=1;
reg present_state, next_state;
always@(posedge clk)begin
if(reset)
present_state <= B;
else
present_state <= next_state;
end
always @(*) begin
if (reset) begin
next_state = B;
end
else begin
case (present_state)
A :
if(in)
next_state <= A;
else
next_state <= B;
B :
if(in)
next_state <= B;
else
next_state <= A;
default: ;
endcase
end
end
assign out = (present_state) ? 1'b1 : 1'b0;
endmodule3、Simple FSM 2(asynchronous reset)
Problem Statement：
This is a Moore state machine with two states, two inputs, and one output. Implement this state machine.
module top_module(
input clk,
input areset,
input j,
input k,
output out);
parameter OFF=0, ON=1;
reg state, next_state;
always @(*) begin
if(areset)
state <= 0;
else
state <= next_state;
end
always @(posedge clk or posedge areset) begin
if(areset)
next_state <= 0;
else begin
case(state)
1'b0 :
case(j)
1'b0 : next_state <= 1'b0;
1'b1 : next_state <= 1'b1;
default : ;
endcase
1'b1 :
case(k)
1'b0 : next_state <= 1'b1;
1'b1 : next_state <= 1'b0;
default : ;
endcase
endcase
end
end
assign out = (state) ? 1'b1 : 1'b0;
endmodule4、Simple FSM 2(synchronous reset)
Problem Statement：
This is a Moore state machine with two states, two inputs, and one output. Implement this state machine.
module top_module(
input clk,
input reset,
input j,
input k,
output out);
parameter OFF=0, ON=1;
reg state, next_state;
always @(posedge clk) begin
if(reset)
state <= 1'b0;
else
state <= next_state;
end
always @(*) begin
if(reset)
next_state <= 1'b0;
else begin
case(state)
1'b0 :
case(j)
1'b0 : next_state <= 1'b0;
1'b1 : next_state <= 1'b1;
default : ;
endcase
1'b1 :
case(k)
1'b0 : next_state <= 1'b1;
1'b1 : next_state <= 1'b0;
default : ;
endcase
endcase
end
end
assign out = (state) ? 1'b1 : 1'b0;
endmodule5、Simple state transition 3
Problem Statement：
The following is the state transition table for a Moore state machine with one input, one output, and four states. Use the following state encoding: A=2'b00, B=2'b01, C=2'b10, D=2'b11.
Implement only the state transition logic and output logic (the combinational logic portion) for this state machine. Given the current state (
state), compute thenext_stateand output (out) based on the state transition table.
State Next state Output in=0 in=1 A A B 0 B C B 0 C A D 0 D C B 1
module top_module(
input in,
input [1:0] state,
output [1:0] next_state,
output out);
parameter A=0, B=1, C=2, D=3;
always@(*)begin
case(state)
2'b00 :
case(in)
1'b0 : next_state <= 2'b00;
1'b1 : next_state <= 2'b01;
default : ;
endcase
2'b01 :
case(in)
1'b0 : next_state <= 2'b10;
1'b1 : next_state <= 2'b01;
default : ;
endcase
2'b10 :
case(in)
1'b0 : next_state <= 2'b00;
1'b1 : next_state <= 2'b11;
default : ;
endcase
2'b11 :
case(in)
1'b0 : next_state <= 2'b10;
1'b1 : next_state <= 2'b01;
default : ;
endcase
endcase
end
assign out = (state == 2'b11) ? 1'b1 : 1'b0;
endmodule6、Simple one-hot state transition 3
Problem Statement：
The following is the state transition table for a Moore state machine with one input, one output, and four states. Use the following one-hot state encoding: A=4'b0001, B=4'b0010, C=4'b0100, D=4'b1000.
State Next state Output in=0 in=1 A A B 0 B C B 0 C A D 0 D C B 1
module top_module(
input in,
input [3:0] state,
output [3:0] next_state,
output out);
parameter A=0, B=1, C=2, D=3;
assign next_state[A] = ~in & (state[A] | state[C]);
assign next_state[B] = in & (state[A] | state[B] | state[D]);
assign next_state[C] = ~in & (state[B] | state[D]);
assign next_state[D] = in & state[C];
assign out = (state[D]) ? 1'b1 : 1'b0;
endmodule7、Simple FSM 3(asynchronous reset)
Problem Statement：
The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include an asynchronous reset that resets the FSM to state A.
State Next state Output in=0 in=1 A A B 0 B C B 0 C A D 0 D C B 1
module top_module(
input clk,
input in,
input areset,
output out);
parameter A = 2'b00;
parameter B = 2'b01;
parameter C = 2'b10;
parameter D = 2'b11;
reg [1:0]current_state;
reg [1:0]next_state;
always@(posedge clk or posedge areset)begin
if(areset)
current_state <= 2'b00;
else
current_state <= next_state;
end
always@(*)begin
if(areset)
next_state <= 2'b00;
else begin
case(in)
1'b0 :
case(current_state)
2'b00 : next_state <= 2'b00;
2'b01 : next_state <= 2'b10;
2'b10 : next_state <= 2'b00;
2'b11 : next_state <= 2'b10;
default : ;
endcase
1'b1 :
case(current_state)
2'b00 : next_state <= 2'b01;
2'b01 : next_state <= 2'b01;
2'b10 : next_state <= 2'b11;
2'b11 : next_state <= 2'b01;
default : ;
endcase
endcase
end
end
assign out = (current_state == 2'b11) ? 1'b1 : 1'b0;
endmodule
8、Simple FSM 3(synchronous reset)
Problem Statement：
The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include a synchronous reset that resets the FSM to state A. (This is the same problem as Fsm3 but with a synchronous reset.)
State Next state Output in=0 in=1 A A B 0 B C B 0 C A D 0 D C B 1
module top_module(
input clk,
input in,
input reset,
output out);
parameter A = 2'b00;
parameter B = 2'b01;
parameter C = 2'b10;
parameter D = 2'b11;
reg[1:0]current_state;
reg[1:0]next_state;
always@(posedge clk)begin
if(reset)
current_state <= 2'b00;
else
current_state <= next_state;
end
always@(*)begin
if(reset)
next_state <= 2'b00;
else begin
case(in)
1'b0 :
case(current_state)
2'b00 : next_state <= 2'b00;
2'b01 : next_state <= 2'b10;
2'b10 : next_state <= 2'b00;
2'b11 : next_state <= 2'b10;
default : ;
endcase
1'b1 :
case(current_state)
2'b00 : next_state <= 2'b01;
2'b01 : next_state <= 2'b01;
2'b10 : next_state <= 2'b11;
2'b11 : next_state <= 2'b01;
default : ;
endcase
endcase
end
end
assign out = (current_state == 2'b11) ? 1'b1 : 1'b0;
endmodule9、Design a Moore FSM
Problem Statement：
Also include an active-high synchronous reset that resets the state machine to a state equivalent to if the water level had been low for a long time (no sensors asserted, and all four outputs asserted).
module top_module (
input clk,
input reset,
input [3:1] s,
output fr3,
output fr2,
output fr1,
output dfr
);
reg [3:0] current_sensor;
reg [3:0] next_sensor;
parameter s1 = 4'b0001;
parameter s1_s2 = 4'b0010;
parameter s2_s3 = 4'b0100;
parameter s3 = 4'b1000;
always@(posedge clk)begin
if(reset)
current_sensor <= s1;
else
current_sensor <= next_sensor;
end
always@(*)begin
if(reset)
next_sensor <= s1;
else begin
case(current_sensor)
s1 :
if(s == 3'b001)
next_sensor <= s1_s2;
else
next_sensor <= s1;
s1_s2 :
if(s == 3'b011)
next_sensor <= s2_s3;
else if(s == 3'b000)
next_sensor <= s1;
else
next_sensor <= s1_s2;
s2_s3 :
if(s == 3'b111)
next_sensor <= s3;
else if(s == 3'b001)
next_sensor <= s1_s2;
else if(s == 3'b000)
next_sensor <= s1;
else
next_sensor <= s2_s3;
s3 :
if(s == 3'b011)
next_sensor <= s2_s3;
else if(s == 3'b001)
next_sensor <= s1_s2;
else if(s == 3'b000)
next_sensor <= s1;
else
next_sensor <= s3;
default : ;
endcase
end
end
always@(posedge clk)begin
if(reset)begin
fr3 <= 1'b1;
fr2 <= 1'b1;
fr1 <= 1'b1;
dfr <= 1'b1;
end
else begin
case(next_sensor)
s1 : begin
fr3 <= 1'b1;
fr2 <= 1'b1;
fr1 <= 1'b1;
dfr <= 1'b1;
end
s1_s2 : begin
fr3 <= 1'b0;
fr2 <= 1'b1;
fr1 <= 1'b1;
if(current_sensor == s1)
dfr <= 1'b0;
else if(current_sensor == s1_s2)
dfr <= dfr;
else
dfr <= 1'b1;
end
s2_s3 : begin
fr3 <= 1'b0;
fr2 <= 1'b0;
fr1 <= 1'b1;
if(current_sensor == s1)
dfr <= 1'b0;
else if(current_sensor == s1_s2)
dfr <= 1'b0;
else if(current_sensor == s2_s3)
dfr <= dfr;
else
dfr <= 1'b1;
end
s3 : begin
fr3 <= 1'b0;
fr2 <= 1'b0;
fr1 <= 1'b0;
if(current_sensor == s2_s3)
dfr <= 1'b0;
else
dfr <= dfr;
end
default : begin
fr3 <= 1'b1;
fr2 <= 1'b1;
fr1 <= 1'b1;
dfr <= 1'b1;
end
endcase
end
end
endmodule
10、Lemmings 1
Problem Statement：
The game Lemmings involves critters with fairly simple brains. So simple that we are going to model it using a finite state machine.
In the Lemmings' 2D world, Lemmings can be in one of two states: walking left or walking right. It will switch directions if it hits an obstacle. In particular, if a Lemming is bumped on the left, it will walk right. If it's bumped on the right, it will walk left. If it's bumped on both sides at the same time, it will still switch directions.
Implement a Moore state machine with two states, two inputs, and one output that models this behaviour.
module top_module(
input clk,
input areset,
input bump_left,
input bump_right,
output walk_left,
output walk_right);
parameter left = 0;
parameter right = 1;
reg state, next_state;
always @(posedge clk or posedge areset)begin
if(areset)
state <= left;
else
state <= next_state;
end
always @(*) begin
if(areset)
next_state <= left;
else begin
case(state)
0 : case(bump_left)
0 : next_state <= left;
1 : next_state <= right;
default : ;
endcase
1 : case(bump_right)
0 : next_state <= right;
1 : next_state <= left;
endcase
default : ;
endcase
end
end
always@(posedge clk or posedge areset)begin
if(areset)begin
walk_left <= 1'b1;
walk_right <= 1'b0;
end
else begin
case(next_state)
left :
begin
walk_left <= 1'b1;
walk_right <= 1'b0;
end
right :
begin
walk_left <= 1'b0;
walk_right <= 1'b1;
end
default :
begin
walk_left <= 1'b1;
walk_right <= 1'b0;
end
endcase
end
end
endmodule
11、Lemmings 2
Problem Statement：
In addition to walking left and right, Lemmings will fall (and presumably go "aaah!") if the ground disappears underneath them.
In addition to walking left and right and changing direction when bumped, when ground=0, the Lemming will fall and say "aaah!". When the ground reappears (ground=1), the Lemming will resume walking in the same direction as before the fall. Being bumped while falling does not affect the walking direction, and being bumped in the same cycle as ground disappears (but not yet falling), or when the ground reappears while still falling, also does not affect the walking direction.
module top_module(
input clk,
input areset,
input bump_left,
input bump_right,
input ground,
output walk_left,
output walk_right,
output aaah
);
reg [3:0]current_state;
reg [3:0]next_state;
parameter left = 4'b0001;
parameter right = 4'b0010;
parameter fall_left = 4'b0100;
parameter fall_right = 4'b1000;
always@(posedge clk or posedge areset)begin
if(areset)
current_state <= left;
else
current_state <= next_state;
end
always@(*)begin
if(areset)
next_state <= left;
else begin
case(ground)
1'b1 :
case(current_state)
left :
case(bump_left)
1'b1 : next_state <= right;
1'b0 : next_state <= left;
default : ;
endcase
right :
case(bump_right)
1'b1 : next_state <= left;
1'b0 : next_state <= right;
default : ;
endcase
fall_left :
next_state <= left;
fall_right :
next_state <= right;
default : ;
endcase
1'b0 :
case(current_state)
left :
next_state <= fall_left;
right :
next_state <= fall_right;
fall_left :
next_state <= fall_left;
fall_right :
next_state <= fall_right;
default : ;
endcase
endcase
end
end
always@(posedge clk or posedge areset)begin
if(areset)begin
walk_left <= 1'b1;
walk_right <= 1'b0;
aaah <= 1'b0;
end
else begin
case(next_state)
left : begin
walk_left <= 1'b1;
walk_right <= 1'b0;
aaah <= 1'b0;
end
right : begin
walk_left <= 1'b0;
walk_right <= 1'b1;
aaah <= 1'b0;
end
fall_left : begin
walk_left <= 1'b0;
walk_right <= 1'b0;
aaah <= 1'b1;
end
fall_right : begin
walk_left <= 1'b0;
walk_right <= 1'b0;
aaah <= 1'b1;
end
default : begin
walk_left <= 1'b1;
walk_right <= 1'b0;
aaah <= 1'b0;
end
endcase
end
end
endmodule12、Lemmings 3
Problem Statement：
In addition to walking and falling, Lemmings can sometimes be told to do useful things, like dig (it starts digging when dig=1). A Lemming can dig if it is currently walking on ground (ground=1 and not falling), and will continue digging until it reaches the other side (ground=0). At that point, since there is no ground, it will fall (aaah!), then continue walking in its original direction once it hits ground again. As with falling, being bumped while digging has no effect, and being told to dig when falling or when there is no ground is ignored.
(In other words, a walking Lemming can fall, dig, or switch directions. If more than one of these conditions are satisfied, fall has higher precedence than dig, which has higher precedence than switching directions.)
module top_module(
input clk,
input areset,
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
parameter left = 3'b000;
parameter right = 3'b001;
parameter fall_left = 3'b010;
parameter fall_right = 3'b011;
parameter dig_left = 3'b100;
parameter dig_right = 3'b101;
reg[2:0]current_state;
reg[2:0]next_state;
always@(posedge clk or posedge areset)begin
if(areset)
current_state <= left;
else
current_state <= next_state;
end
always@(*)begin
if(areset)
next_state <= left;
else begin
case(current_state)
left : begin
if(!ground)
next_state <= fall_left;
else if(dig)
next_state <= dig_left;
else if(bump_left)
next_state <= right;
else
next_state <= left;
end
right : begin
if(!ground)
next_state <= fall_right;
else if(dig)
next_state <= dig_right;
else if(bump_right)
next_state <= left;
else
next_state <= right;
end
fall_left : begin
if(ground)
next_state <= left;
else
next_state <= fall_left;
end
fall_right : begin
if(ground)
next_state <= right;
else
next_state <= fall_right;
end
dig_left : begin
if(!ground)
next_state <= fall_left;
else
next_state <= dig_left;
end
dig_right : begin
if(!ground)
next_state <= fall_right;
else
next_state <= dig_right;
end
default : ;
endcase
end
end
always@(posedge clk or posedge areset)begin
if(areset)begin
walk_left <= 1'b1;
walk_right <= 1'b0;
aaah <= 1'b0;
digging <= 1'b0;
end
else begin
case(next_state)
left : begin
walk_left <= 1'b1;
walk_right <= 1'b0;
aaah <= 1'b0;
digging <= 1'b0;
end
right : begin
walk_left <= 1'b0;
walk_right <= 1'b1;
aaah <= 1'b0;
digging <= 1'b0;
end
fall_left : begin
walk_left <= 1'b0;
walk_right <= 1'b0;
aaah <= 1'b1;
digging <= 1'b0;
end
fall_right : begin
walk_left <= 1'b0;
walk_right <= 1'b0;
aaah <= 1'b1;
digging <= 1'b0;
end
dig_left : begin
walk_left <= 1'b0;
walk_right <= 1'b0;
aaah <= 1'b0;
digging <= 1'b1;
end
dig_right : begin
walk_left <= 1'b0;
walk_right <= 1'b0;
aaah <= 1'b0;
digging <= 1'b1;
end
default : ;
endcase
end
end
endmodule
13、Lemmings 4
Problem Statement：
Although Lemmings can walk, fall, and dig, Lemmings aren't invulnerable. If a Lemming falls for too long then hits the ground, it can splatter. In particular, if a Lemming falls for more than 20 clock cycles then hits the ground, it will splatter and cease walking, falling, or digging (all 4 outputs become 0), forever (Or until the FSM gets reset). There is no upper limit on how far a Lemming can fall before hitting the ground. Lemmings only splatter when hitting the ground; they do not splatter in mid-air.
Extend your finite state machine to model this behaviour.
Falling for 20 cycles is survivable:
Falling for 21 cycles causes splatter:
module top_module(
input clk,
input areset,
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
parameter left = 3'b000;
parameter right = 3'b001;
parameter fall_left = 3'b010;
parameter fall_right = 3'b011;
parameter dig_left = 3'b100;
parameter dig_right = 3'b101;
parameter splatter = 3'b110;
reg[2:0]current_state;
reg[2:0]next_state;
reg[9:0]cnt;
always@(posedge clk or posedge areset)begin
if(areset)
cnt <= 5'b0;
else if(!ground)
cnt <= cnt + 1'b1;
else if(ground)
cnt <= 10'd0;
end
always@(posedge clk or posedge areset)begin
if(areset)
current_state <= left;
else
current_state <= next_state;
end
always@(*)begin
if(areset)
next_state <= left;
else begin
case(current_state)
left : begin
if(!ground)
next_state <= fall_left;
else if(dig)
next_state <= dig_left;
else if(bump_left)
next_state <= right;
else
next_state <= left;
end
right : begin
if(!ground)
next_state <= fall_right;
else if(dig)
next_state <= dig_right;
else if(bump_right)
next_state <= left;
else
next_state <= right;
end
fall_left : begin
if(ground)begin
if(cnt > 5'd20)
next_state <= splatter;
else
next_state <= left;
end
else
next_state <= fall_left;
end
fall_right : begin
if(ground)begin
if(cnt > 5'd20)
next_state <= splatter;
else
next_state <= right;
end
else
next_state <= fall_right;
end
dig_left : begin
if(!ground)
next_state <= fall_left;
else
next_state <= dig_left;
end
dig_right : begin
if(!ground)
next_state <= fall_right;
else
next_state <= dig_right;
end
splatter : begin
if(areset)
next_state <= left;
else
next_state <= splatter;
end
default : ;
endcase
end
end
always@(posedge clk or posedge areset)begin
if(areset)begin
walk_left <= 1'b1;
walk_right <= 1'b0;
aaah <= 1'b0;
digging <= 1'b0;
end
else begin
case(next_state)
left : begin
walk_left <= 1'b1;
walk_right <= 1'b0;
aaah <= 1'b0;
digging <= 1'b0;
end
right : begin
walk_left <= 1'b0;
walk_right <= 1'b1;
aaah <= 1'b0;
digging <= 1'b0;
end
fall_left : begin
walk_left <= 1'b0;
walk_right <= 1'b0;
aaah <= 1'b1;
digging <= 1'b0;
end
fall_right : begin
walk_left <= 1'b0;
walk_right <= 1'b0;
aaah <= 1'b1;
digging <= 1'b0;
end
dig_left : begin
walk_left <= 1'b0;
walk_right <= 1'b0;
aaah <= 1'b0;
digging <= 1'b1;
end
dig_right : begin
walk_left <= 1'b0;
walk_right <= 1'b0;
aaah <= 1'b0;
digging <= 1'b1;
end
splatter : begin
walk_left <= 1'b0;
walk_right <= 1'b0;
aaah <= 1'b0;
digging <= 1'b0;
end
default : ;
endcase
end
end
endmodule
14、One-hot FSM
Problem Statement：
Given the following state machine with 1 input and 2 outputs:
Suppose this state machine uses one-hot encoding, where state[0] through state[9] correspond to the states S0 though S9, respectively. The outputs are zero unless otherwise specified.
Implement the state transition logic and output logic portions of the state machine (but not the state flip-flops). You are given the current state in state[9:0] and must produce next_state[9:0] and the two outputs. Derive the logic equations by inspection assuming a one-hot encoding. (The testbench will test with non-one hot inputs to make sure you're not trying to do something more complicated).
module top_module(
input in,
input [9:0] state,
output [9:0] next_state,
output out1,
output out2
);
parameter S0 = 4'd0;
parameter S1 = 4'd1;
parameter S2 = 4'd2;
parameter S3 = 4'd3;
parameter S4 = 4'd4;
parameter S5 = 4'd5;
parameter S6 = 4'd6;
parameter S7 = 4'd7;
parameter S8 = 4'd8;
parameter S9 = 4'd9;
assign next_state[S0] = (state[S0] & ~in) | (state[S1] & ~in) | (state[S2] & ~in) | (state[S3] & ~in) | (state[S4] & ~in) | (state[S7] & ~in) | (state[S8] & ~in) | (state[S9] & ~in);
assign next_state[S1] = (state[S0] & in) | (state[S8] & in) | (state[S9] & in);
assign next_state[S2] = (state[S1] & in);
assign next_state[S3] = (state[S2] & in);
assign next_state[S4] = (state[S3] & in);
assign next_state[S5] = (state[S4] & in);
assign next_state[S6] = (state[S5] & in);
assign next_state[S7] = (state[S6] & in) | (state[S7] & in);
assign next_state[S8] = (state[S5] & ~in);
assign next_state[S9] = (state[S6] & ~in);
assign out1 = state[S8] | state[S9];
assign out2 = state[S7] | state[S9];
endmodule
15、PS/2 packet parser
Problem Statement：
The PS/2 mouse protocol sends messages that are three bytes long. However, within a continuous byte stream, it's not obvious where messages start and end. The only indication is that the first byte of each three byte message always has bit[3]=1 (but bit[3] of the other two bytes may be 1 or 0 depending on data).
We want a finite state machine that will search for message boundaries when given an input byte stream. The algorithm we'll use is to discard bytes until we see one with bit[3]=1. We then assume that this is byte 1 of a message, and signal the receipt of a message once all 3 bytes have been received (done).
The FSM should signal done in the cycle immediately after the third byte of each message was successfully received.
Some timing diagrams to explain the desired behaviour
Under error-free conditions, every three bytes form a message:
When an error occurs, search for byte 1:
Note that this is not the same as a 1xx sequence recognizer. Overlapping sequences are not allowed here:
module top_module(
input clk,
input [7:0] in,
input reset,
output done
);
parameter b1 = 4'b0001;
parameter b2 = 4'b0010;
parameter b3 = 4'b0100;
parameter finish = 4'b1000;
reg[3:0]current_state;
reg[3:0]next_state;
always@(posedge clk)begin
if(reset)
current_state <= b1;
else
current_state <= next_state;
end
always@(*)begin
if(reset)
next_state <= b1;
else begin
case(current_state)
b1 : begin
if(in[3])
next_state <= b2;
else
next_state <= b1;
end
b2 :
next_state <= b3;
b3 :
next_state <= finish;
finish : begin
if(in[3])
next_state <= b2;
else
next_state <= b1;
end
default : ;
endcase
end
end
always@(posedge clk)begin
if(reset)
done <= 1'b0;
else begin
case(next_state)
b1 : done <= 1'b0;
b2 : done <= 1'b0;
b3 : done <= 1'b0;
finish: done <= 1'b1;
default:done <= 1'b0;
endcase
end
end
endmodule
16、PS/2 packet parser and datapath
Problem Statement：
Now that you have a state machine that will identify three-byte messages in a PS/2 byte stream, add a datapath that will also output the 24-bit (3 byte) message whenever a packet is received (out_bytes[23:16] is the first byte, out_bytes[15:8] is the second byte, etc.).
out_bytes needs to be valid whenever the done signal is asserted. You may output anything at other times (i.e., don't-care).
For example:
module top_module(
input clk,
input [7:0] in,
input reset,
output [23:0] out_bytes,
output done);
parameter b1 = 4'b0001;
parameter b2 = 4'b0010;
parameter b3 = 4'b0100;
parameter finish = 4'b1000;
reg[3:0]current_state;
reg[3:0]next_state;
always@(posedge clk)begin
if(reset)
current_state <= b1;
else
current_state <= next_state;
end
always@(*)begin
if(reset)
next_state <= b1;
else begin
case(current_state)
b1 : begin
if(in[3])
next_state <= b2;
else
next_state <= b1;
end
b2 :
next_state <= b3;
b3 :
next_state <= finish;
finish : begin
if(in[3])
next_state <= b2;
else
next_state <= b1;
end
default : ;
endcase
end
end
always@(posedge clk)begin
if(reset)
done <= 1'b0;
else begin
case(next_state)
b1,b2,b3 : begin
done <= 1'b0;
out_bytes <= {out_bytes[15:0],in[7:0]};
end
finish: begin
done <= 1'b1;
out_bytes <= {out_bytes[15:0],in[7:0]};
end
default:done <= 1'b0;
endcase
end
end
endmodule
16、Serial receiver
Problem Statement：
In many (older) serial communications protocols, each data byte is sent along with a start bit and a stop bit, to help the receiver delimit bytes from the stream of bits. One common scheme is to use one start bit (0), 8 data bits, and 1 stop bit (1). The line is also at logic 1 when nothing is being transmitted (idle).
Design a finite state machine that will identify when bytes have been correctly received when given a stream of bits. It needs to identify the start bit, wait for all 8 data bits, then verify that the stop bit was correct. If the stop bit does not appear when expected, the FSM must wait until it finds a stop bit before attempting to receive the next byte.
Some timing diagrams
Error-free:
Stop bit not found. First byte is discarded:
module top_module(
input clk,
input in,
input reset,
output done
);
parameter idle = 4'b0001;
parameter data = 4'b0010;
parameter finish = 4'b0100;
parameter error = 4'b1000;
reg[3:0]current_state;
reg[3:0]next_state;
reg[3:0]cnt;
always@(posedge clk)begin
if(reset)
cnt <= 4'b0;
else if(current_state == data)
cnt <= cnt + 1'b1;
else
cnt <= 4'd0;
end
always@(posedge clk)begin
if(reset)
current_state <= idle;
else
current_state <= next_state;
end
always@(*)begin
if(reset)
next_state <= idle;
else begin
case(current_state)
idle : begin
if(!in)
next_state <= data;
else
next_state <= idle;
end
data : begin
if(cnt == 4'd8)
case(in)
1'b1 : next_state <= finish;
1'b0 : next_state <= error;
endcase
else
next_state <= data;
end
finish : begin
if(!in)
next_state <= data;
else
next_state <= idle;
end
error : begin
if(!in)
next_state <= error;
else
next_state <= idle;
end
endcase
end
end
always@(posedge clk)begin
if(reset)
done <= 1'b0;
else
case(next_state)
finish : done <= 1'b1;
default : done <= 1'b0;
endcase
end
endmodule
17、Serial receiver and datapath
Problem Statement：
Now that you have a finite state machine that can identify when bytes are correctly received in a serial bitstream, add a datapath that will output the correctly-received data byte. out_byte needs to be valid when done is 1, and is don't-care otherwise.
Note that the serial protocol sends the least significant bit first.
Some timing diagrams
Error-free:
module top_module(
input clk,
input in,
input reset,
output [7:0] out_byte,
output done
);
parameter idle = 4'b0001;
parameter data = 4'b0010;
parameter finish = 4'b0100;
parameter error = 4'b1000;
reg[3:0]current_state;
reg[3:0]next_state;
reg[3:0]cnt;
reg[7:0]temp_byte;
always@(posedge clk)begin
if(reset)
cnt <= 4'b0;
else if(current_state == data)
cnt <= cnt + 1'b1;
else
cnt <= 4'd0;
end
always@(posedge clk)begin
if(reset)
temp_byte <= 8'b0;
else
case(next_state)
data : temp_byte <= {in,temp_byte[7:1]};
default : temp_byte <= temp_byte;
endcase
end
always@(posedge clk)begin
if(reset)
current_state <= idle;
else
current_state <= next_state;
end
always@(*)begin
if(reset)
next_state <= idle;
else begin
case(current_state)
idle : begin
if(!in)
next_state <= data;
else
next_state <= idle;
end
data : begin
if(cnt == 4'd8)
case(in)
1'b1 : next_state <= finish;
1'b0 : next_state <= error;
endcase
else
next_state <= data;
end
finish : begin
if(!in)
next_state <= data;
else
next_state <= idle;
end
error : begin
if(!in)
next_state <= error;
else
next_state <= idle;
end
endcase
end
end
always@(posedge clk)begin
if(reset)
done <= 1'b0;
else
case(next_state)
finish :begin
done <= 1'b1;
out_byte <= temp_byte;
end
default : begin
done <= 1'b0;
out_byte <= 8'b0;
end
endcase
end
endmodule
18、Serial receiver with parity checking
Problem Statement：
We want to add parity checking to the serial receiver. Parity checking adds one extra bit after each data byte. We will use odd parity, where the number of 1s in the 9 bits received must be odd. For example, 101001011 satisfies odd parity (there are 5 1s), but 001001011 does not.
Change your FSM and datapath to perform odd parity checking. Assert the done signal only if a byte is correctly received and its parity check passes. Like the serial receiver FSM, this FSM needs to identify the start bit, wait for all 9 (data and parity) bits, then verify that the stop bit was correct. If the stop bit does not appear when expected, the FSM must wait until it finds a stop bit before attempting to receive the next byte.
You are provided with the following module that can be used to calculate the parity of the input stream (It's a TFF with reset). The intended use is that it should be given the input bit stream, and reset at appropriate times so it counts the number of 1 bits in each byte.
module parity ( input clk, input reset, input in, output reg odd); always @(posedge clk) if (reset) odd <= 0; else if (in) odd <= ~odd; endmoduleNote that the serial protocol sends the least significant bit first, and the parity bit after the 8 data bits.
Some timing diagrams
No framing errors. Odd parity passes for first byte, fails for second byte.
module top_module(
input clk,
input in,
input reset,
output [7:0] out_byte,
output done
);
parameter idle = 4'b0001;
parameter data = 4'b0010;
parameter finish = 4'b0100;
parameter error = 4'b1000;
reg[3:0]current_state;
reg[3:0]next_state;
reg[3:0]cnt;
reg[7:0]temp_byte;
wire odd_check;
wire reset_odd;
assign reset_odd = reset | (!(current_state == data));
always@(posedge clk)begin
if(reset)
cnt <= 4'b0;
else if(current_state == data)
cnt <= cnt + 1'b1;
else
cnt <= 4'd0;
end
always@(posedge clk)begin
if(reset)
temp_byte <= 8'b0;
else if((current_state == data) && (cnt <= 4'd7))
temp_byte <= {in,temp_byte[7:1]};
else
temp_byte <= temp_byte;
end
always@(posedge clk)begin
if(reset)
current_state <= idle;
else
current_state <= next_state;
end
always@(*)begin
if(reset)
next_state <= idle;
else begin
case(current_state)
idle : begin
if(!in)
next_state <= data;
else
next_state <= idle;
end
data : begin
if(cnt == 4'd9)
case(in)
1'b1 : next_state <= finish;
1'b0 : next_state <= error;
endcase
else
next_state <= data;
end
finish : begin
if(!in)
next_state <= data;
else
next_state <= idle;
end
error : begin
if(!in)
next_state <= error;
else
next_state <= idle;
end
endcase
end
end
always@(posedge clk)begin
if(reset)
done <= 1'b0;
else
case(next_state)
finish :begin
if(odd_check)begin
done <= 1'b1;
out_byte <= temp_byte;
end
else begin
done <= 1'b0;
out_byte <= temp_byte;
end
end
default : begin
done <= 1'b0;
out_byte <= 8'b0;
end
endcase
end
parity instance1(.clk(clk), .reset(reset_odd), .in(in), .odd(odd_check));
endmodule
19、Sequence recognition
Problem Statement：
Create a finite state machine to recognize these three sequences:
- 0111110: Signal a bit needs to be discarded (disc).
- 01111110: Flag the beginning/end of a frame (flag).
- 01111111...: Error (7 or more 1s) (err).
When the FSM is reset, it should be in a state that behaves as though the previous input were 0.
Here are some example sequences that illustrate the desired operation.
Discard 0111110:
Flag 01111110:
Reset behaviour and error 01111111...:
module top_module(
input clk,
input reset,
input in,
output disc,
output flag,
output err
);
reg[3:0]current_state;
reg[3:0]next_state;
parameter s0 = 4'd0,
s1 = 4'd1,
s2 = 4'd2,
s3 = 4'd3,
s4 = 4'd4,
s5 = 4'd5,
s6 = 4'd6,
s_disc = 4'd7,
s_flag = 4'd8,
s_error = 4'd9;
always@(posedge clk)begin
if(reset)
current_state <= s0;
else
current_state <= next_state;
end
always@(*)begin
if(reset)
next_state <= s0;
else
case(current_state)
s0 : next_state <= in ? s1 : s0;
s1 : next_state <= in ? s2 : s0;
s2 : next_state <= in ? s3 : s0;
s3 : next_state <= in ? s4 : s0;
s4 : next_state <= in ? s5 : s0;
s5 : next_state <= in ? s6 : s_disc;
s6 : next_state <= in ? s_error : s_flag;
s_disc : next_state <= in ? s1 : s0;
s_flag : next_state <= in ? s1 : s0;
s_error : next_state <= in ? s_error : s0;
default : next_state <= s0;
endcase
end
always@(posedge clk)begin
if(reset)begin
disc <= 1'b0;
flag <= 1'b0;
err <= 1'b0;
end
else begin
case(next_state)
s_disc : begin
disc <= 1'b1;
flag <= 1'b0;
err <= 1'b0;
end
s_flag : begin
disc <= 1'b0;
flag <= 1'b1;
err <= 1'b0;
end
s_error : begin
disc <= 1'b0;
flag <= 1'b0;
err <= 1'b1;
end
default : begin
disc <= 1'b0;
flag <= 1'b0;
err <= 1'b0;
end
endcase
end
end
endmodule
20、Design a Mealy FSM
Problem Statement：
Implement a Mealy-type finite state machine that recognizes the sequence "101" on an input signal named x. Your FSM should have an output signal, z, that is asserted to logic-1 when the "101" sequence is detected. Your FSM should also have an active-low asynchronous reset. You may only have 3 states in your state machine. Your FSM should recognize overlapping sequences.
module top_module (
input clk,
input aresetn,
input x,
output z
);
parameter s0 = 3'b001;
parameter s1 = 3'b010;
parameter s2 = 3'b100;
reg[2:0]current_state;
reg[2:0]next_state;
always@(posedge clk or negedge aresetn)begin
if(!aresetn)
current_state <= s0;
else
current_state <= next_state;
end
always@(*)begin
if(!aresetn)
next_state <= s0;
else
case(current_state)
s0 :
if(x)
next_state <= s1;
else
next_state <= s0;
s1 :
if(x)
next_state <= s1;
else
next_state <= s2;
s2 :
if(x)
next_state <= s1;
else
next_state <= s0;
default : next_state <= s0;
endcase
end
assign z = ((current_state == s2) && (x == 1'b1)) ? 1'b1 : 1'b0;
endmodule
21、Serial two's complementer (Moore FSM)
Problem Statement：
You are to design a one-input one-output serial 2's complementer Moore state machine. The input (x) is a series of bits (one per clock cycle) beginning with the least-significant bit of the number, and the output (Z) is the 2's complement of the input. The machine will accept input numbers of arbitrary length. The circuit requires an asynchronous reset. The conversion begins when Reset is released and stops when Reset is asserted.
For example:
//ref
module top_module (
input clk,
input areset,
input x,
output z
);
parameter A = 2'd0,
B = 2'd1,
C = 2'd2;
reg[1:0] cur_state ,
next_state ;
always @(posedge clk or posedge areset)begin
if(areset)
cur_state <= A;
else
cur_state <= next_state;
end
always@(*)begin
//next_state = A;
case(cur_state)
A : next_state = x ? B : A;
B : next_state = x ? C : B;
C : next_state = x ? C : B;
default : next_state = A;
endcase
end
assign z = (cur_state ==B);
endmodule22、Serial two's complementer (Mealy FSM)
Problem Statement：
The following diagram is a Mealy machine implementation of the 2's complementer. Implement using one-hot encoding.
//ref
module top_module (
input clk,
input areset,
input x,
output z
);
parameter A = 1'd0,
B = 1'd1;
reg cur_state ,
next_state ;
always @(posedge clk or posedge areset)begin
if(areset)
cur_state <= A;
else
cur_state <= next_state;
end
always@(*)begin
next_state = A;
case(cur_state)
A : next_state = x ? B : A;
B : next_state = B;
default : next_state = A;
endcase
end
assign z = (cur_state == A && x) || (cur_state == B && ~x);
endmodule
23、FSM
Problem Statement：
Consider a finite state machine with inputs s and w. Assume that the FSM begins in a reset state called A, as depicted below. The FSM remains in state A as long as s = 0, and it moves to state B when s = 1. Once in state B the FSM examines the value of the input w in the next three clock cycles. If w = 1 in exactly two of these clock cycles, then the FSM has to set an output z to 1 in the following clock cycle. Otherwise z has to be 0. The FSM continues checking w for the next three clock cycles, and so on. The timing diagram below illustrates the required values of z for different values of w.
Use as few states as possible. Note that the s input is used only in state A, so you need to consider just the w input.
module top_module (
input clk,
input reset,
input s,
input w,
output z
);
parameter A = 2'b01,
B = 2'b10;
reg[1:0]current_state;
reg[1:0]next_state;
reg[2:0]cnt_w1;
always@(posedge clk)begin
if(reset)
cnt_w1 <= 3'd0;
else if(current_state == B)begin
if(cnt_w1 == 3'd2)
cnt_w1 <= 3'd0;
else
cnt_w1 <= cnt_w1 + 1'b1;
end
end
reg[2:0]cnt_w2;
always@(posedge clk)begin
if(reset)
cnt_w2 <= 3'd0;
else if(current_state == B)begin
if(cnt_w1 == 3'd2)
cnt_w2 <= 3'd0;
else if(w)
cnt_w2 <= cnt_w2 + 1'b1;
else
cnt_w2 <= cnt_w2;
end
end
always@(posedge clk)begin
if(reset)
current_state <= A;
else
current_state <= next_state;
end
always@(*)begin
if(reset)
next_state <= A;
else
case(current_state)
A : case(s)
1'b0 : next_state <= A;
1'b1 : next_state <= B;
default : next_state <= A;
endcase
B : next_state <= B;
default : next_state <= A;
endcase
end
always@(posedge clk)begin
if(reset)
z <= 1'b0;
else
case(current_state)
B : begin
if(cnt_w1 == 3'd2)begin
case((cnt_w2 == 3'd1 && w) || (cnt_w2 == 3'd2 && !w))
1'b1 : z <= 1'b1;
default : z <= 1'b0;
endcase
end
else
z <= 1'b0;
end
default : z <= 1'b0;
endcase
end
endmodule
24、FSM
Problem Statement：
Given the state-assigned table shown below, implement the finite-state machine. Reset should reset the FSM to state 000.
Present state
y[2:0]Next state Y[2:0] Output z x=0 x=1 000 000 001 0 001 001 100 0 010 010 001 0 011 001 010 1 100 011 100 1
module top_module (
input clk,
input reset,
input x,
output z
);
parameter s0 = 3'b000,
s1 = 3'b001,
s2 = 3'b010,
s3 = 3'b011,
s4 = 3'b100;
reg[2:0]current_state;
reg[2:0]next_state;
always@(posedge clk)begin
if(reset)
current_state <= s0;
else
current_state <= next_state;
end
always@(*)begin
if(reset)
next_state <= s0;
else
case(current_state)
s0 : next_state <= x ? s1 : s0;
s1 : next_state <= x ? s4 : s1;
s2 : next_state <= x ? s1 : s2;
s3 : next_state <= x ? s2 : s1;
s4 : next_state <= x ? s4 : s3;
default : next_state <= s0;
endcase
end
always@(posedge clk)begin
if(reset)
z <= 1'b0;
else
case(next_state)
s0 : z <= 1'b0;
s1 : z <= 1'b0;
s2 : z <= 1'b0;
s3 : z <= 1'b1;
s4 : z <= 1'b1;
default : z <= 1'b0;
endcase
end
endmodule
25、FSM logic
Problem Statement：
Given the state-assigned table shown below, implement the logic functions Y[0] and z.
Present state
y[2:0]Next state Y[2:0] Output z x=0 x=1 000 000 001 0 001 001 100 0 010 010 001 0 011 001 010 1 100 011 100 1
module top_module (
input clk,
input [2:0] y,
input x,
output Y0,
output z
);
parameter s0 = 3'b000,
s1 = 3'b001,
s2 = 3'b010,
s3 = 3'b011,
s4 = 3'b100;
reg[2:0]next_state;
always@(*)begin
case(y)
s0 : next_state <= x ? s1 : s0;
s1 : next_state <= x ? s4 : s1;
s2 : next_state <= x ? s1 : s2;
s3 : next_state <= x ? s2 : s1;
s4 : next_state <= x ? s4 : s3;
default : next_state <= s0;
endcase
end
assign Y0 = (next_state == s1 || next_state == s3);
assign z = (y == s3 || y == s4);
endmodule
26、FSM next_state logic
Problem Statement：
Consider the state machine shown below, which has one input w and one output z.
Assume that you wish to implement the FSM using three flip-flops and state codes y[3:1] = 000, 001, ... , 101 for states A, B, ... , F, respectively. Show a state-assigned table for this FSM. Derive a next-state expression for the flip-flop y[2].
Implement just the next-state logic for y[2].
module top_module (
input [3:1] y,
input w,
output Y2);
parameter s0 = 3'b000,
s1 = 3'b001,
s2 = 3'b010,
s3 = 3'b011,
s4 = 3'b100,
s5 = 3'b101;
reg[2:0]next_state;
always@(*)begin
case(y)
s0 : next_state <= w ? s0 : s1;
s1 : next_state <= w ? s3 : s2;
s2 : next_state <= w ? s3 : s4;
s3 : next_state <= w ? s0 : s5;
s4 : next_state <= w ? s3 : s4;
s5 : next_state <= w ? s3 : s2;
default : next_state <= s0;
endcase
end
assign Y2 = next_state[1];
endmodule
27、FSM one-hot next_state logic
Problem Statement：
Consider the state machine shown below, which has one input w and one output z.
For this part, assume that a one-hot code is used with the state assignment 'y[6:1] = 000001, 000010, 000100, 001000, 010000, 100000 for states A, B,..., F, respectively.
Write a logic expression for the next-state signals Y2 and Y4. (Derive the logic equations by inspection assuming a one-hot encoding. The testbench will test with non-one hot inputs to make sure you're not trying to do something more complicated).
//error
module top_module (
input [6:1] y,
input w,
output Y2,
output Y4);
parameter s0 = 6'b000001,
s1 = 6'b000010,
s2 = 6'b000100,
s3 = 6'b001000,
s4 = 6'b010000,
s5 = 6'b100000;
reg[5:0]next_state;
always@(*)begin
case(y)
s0 : next_state <= w ? s0 : s1;
s1 : next_state <= w ? s3 : s2;
s2 : next_state <= w ? s3 : s4;
s3 : next_state <= w ? s0 : s5;
s4 : next_state <= w ? s3 : s4;
s5 : next_state <= w ? s3 : s2;
default : next_state <= s0;
endcase
end
assign Y2 = next_state[1];
assign Y4 = next_state[3];
endmodule
//ref
module top_module (
input [6:1] y,
input w,
output Y2,
output Y4);
parameter A = 3'd1, B = 3'd2, C = 3'd3;
parameter D = 3'd4, E = 3'd5, F = 3'd6;
assign Y2 = ~w & y[A];
assign Y4 = w & (y[B] | y[C] | y[E] | y[F]);
endmodule
28、FSM
Problem Statement：
Consider the state machine shown below, which has one input w and one output z.
Implement the state machine. (This part wasn't on the midterm, but coding up FSMs is good practice).
module top_module (
input clk,
input reset,
input w,
output z);
parameter s0 = 3'b000,
s1 = 3'b001,
s2 = 3'b010,
s3 = 3'b011,
s4 = 3'b100,
s5 = 3'b101;
reg [2:0]current_state;
reg [2:0]next_state;
always @(posedge clk)begin
if(reset)
current_state <= s0;
else
current_state <= next_state;
end
always@(*)begin
next_state = s0;
case(current_state)
s0 : next_state <= w ? s0 : s1;
s1 : next_state <= w ? s3 : s2;
s2 : next_state <= w ? s3 : s4;
s3 : next_state <= w ? s0 : s5;
s4 : next_state <= w ? s3 : s4;
s5 : next_state <= w ? s3 : s2;
default : next_state = s0;
endcase
end
always @(posedge clk)begin
if(reset)
z<= 1'b0;
else
case(next_state)
s0 : z<= 1'b0;
s1 : z<= 1'b0;
s2 : z<= 1'b0;
s3 : z<= 1'b0;
s4 : z<= 1'b1;
s5 : z<= 1'b1;
default : z<= 1'b0;
endcase
end
endmodule29、FSM
Problem Statement：
Consider the state diagram shown below.
Write complete Verilog code that represents this FSM. Use separate always blocks for the state table and the state flip-flops, as done in lectures. Describe the FSM output, which is called z, using either continuous assignment statement(s) or an always block (at your discretion). Assign any state codes that you wish to use.
module top_module (
input clk,
input reset,
input w,
output z
);
parameter A = 3'b000,
B = 3'b001,
C = 3'b010,
D = 3'b011,
E = 3'b100,
F = 3'b101;
reg[2:0]current_state;
reg[2:0]next_state;
always@(posedge clk)begin
if(reset)
current_state <= A;
else
current_state <= next_state;
end
always@(*)begin
if(reset)
next_state <= A;
else
case(current_state)
A : next_state <= w ? B : A;
B : next_state <= w ? C : D;
C : next_state <= w ? E : D;
D : next_state <= w ? F : A;
E : next_state <= w ? E : D;
F : next_state <= w ? C : D;
default : next_state <=A;
endcase
end
always@(posedge clk)begin
if(reset)
z <= 1'b0;
else
case(next_state)
A : z <= 1'b0;
B : z <= 1'b0;
C : z <= 1'b0;
D : z <= 1'b0;
E : z <= 1'b1;
F : z <= 1'b1;
default : z <= 1'b0;
endcase
end
endmodule
30、one-hot FSM equation
Problem Statement：
The state diagram for this question is shown again below.
Assume that a one-hot code is used with the state assignment y[5:0] = 000001(A), 000010(B), 000100(C), 001000(D), 010000(E), 100000(F)
Write a logic expression for the signal Y1, which is the input of state flip-flop y[1].
Write a logic expression for the signal Y3, which is the input of state flip-flop y[3].
(Derive the logic equations by inspection assuming a one-hot encoding. The testbench will test with non-one hot inputs to make sure you're not trying to do something more complicated).
//error
module top_module (
input [5:0] y,
input w,
output Y1,
output Y3
);
parameter A = 6'b000001,
B = 6'b000010,
C = 6'b000100,
D = 6'b001000,
E = 6'b010000,
F = 6'b100000;
reg[5:0]next_state;
always@(*)begin
case(y)
A : next_state <= w ? B : A;
B : next_state <= w ? C : D;
C : next_state <= w ? E : D;
D : next_state <= w ? F : A;
E : next_state <= w ? E : D;
F : next_state <= w ? C : D;
default : next_state <=A;
endcase
end
assign Y1 = next_state[1];
assign Y3 = next_state[3];
endmodule
//ref
module top_module (
input [5:0] y,
input w,
output Y1,
output Y3
);
parameter A = 3'd0, B = 3'd1, C = 3'd2;
parameter D = 3'd3, E = 3'd4, F = 3'd5;
assign Y1 = w & y[A];
assign Y3 = ~w & (y[B] | y[C] | y[E] | y[F]);
endmodule31、FSM
Problem Statement：
Consider the FSM described by the state diagram shown below:
This FSM acts as an arbiter circuit, which controls access to some type of resource by three requesting devices. Each device makes its request for the resource by setting a signal r[i] = 1, where r[i] is either r[1], r[2], or r[3]. Each r[i] is an input signal to the FSM, and represents one of the three devices. The FSM stays in state A as long as there are no requests. When one or more request occurs, then the FSM decides which device receives a grant to use the resource and changes to a state that sets that device’s g[i] signal to 1. Each g[i] is an output from the FSM. There is a priority system, in that device 1 has a higher priority than device 2, and device 3 has the lowest priority. Hence, for example, device 3 will only receive a grant if it is the only device making a request when the FSM is in state A. Once a device, i, is given a grant by the FSM, that device continues to receive the grant as long as its request, r[i] = 1.
Write complete Verilog code that represents this FSM. Use separate always blocks for the state table and the state flip-flops, as done in lectures. Describe the FSM outputs, g[i], using either continuous assignment statement(s) or an always block (at your discretion). Assign any state codes that you wish to use.
module top_module (
input clk,
input resetn,
input [3:1] r,
output [3:1] g
);
parameter A = 4'b0001,
B = 4'b0010,
C = 4'b0100,
D = 4'b1000;
reg[3:0]current_state;
reg[3:0]next_state;
always @(posedge clk)begin
if(!resetn)
current_state <= A;
else
current_state <= next_state;
end
always@(*)begin
next_state = A;
case(current_state)
A : begin
if(r[1])
next_state = B;
else if(r[2])
next_state = C;
else if(r[3])
next_state = D;
else
next_state = A;
end
B : begin
if(r[1])
next_state = B;
else
next_state = A;
end
C : begin
if(r[2])
next_state = C;
else
next_state = A;
end
D : begin
if(r[3])
next_state = D;
else
next_state = A;
end
default : next_state = A;
endcase
end
assign g[1] = (current_state == B);
assign g[2] = (current_state == C);
assign g[3] = (current_state == D);
endmodule32、Another FSM
Problem Statement：
Consider a finite state machine that is used to control some type of motor. The FSM has inputs x and y, which come from the motor, and produces outputs f and g, which control the motor. There is also a clock input called clk and a reset input called resetn.
The FSM has to work as follows. As long as the reset input is asserted, the FSM stays in a beginning state, called state A. When the reset signal is de-asserted, then after the next clock edge the FSM has to set the output f to 1 for one clock cycle. Then, the FSM has to monitor the x input. When x has produced the values 1, 0, 1 in three successive clock cycles, then g should be set to 1 on the following clock cycle. While maintaining g = 1 the FSM has to monitor the y input. If y has the value 1 within at most two clock cycles, then the FSM should maintain g = 1 permanently (that is, until reset). But if y does not become 1 within two clock cycles, then the FSM should set g = 0 permanently (until reset).
(The original exam question asked for a state diagram only. But here, implement the FSM.)
module top_module (
input clk,
input resetn,
input x,
input y,
output f,
output g
);
parameter start = 4'b0001,
out_f = 4'b0010,
mon_x = 4'b0011,
s0 = 4'b0100,
s1 = 4'b0101,
s2 = 4'b0110,
jug = 4'b0111,
p1 = 4'b1000,
p0 = 4'b1001;
reg[3:0]current_state;
reg[3:0]next_state;
always@(posedge clk)begin
if(!resetn)
current_state <= start;
else
current_state <= next_state;
end
always@(*)begin
if(!resetn)
next_state <= start;
else
case(current_state)
start : next_state <= out_f;
out_f : next_state <= mon_x;
mon_x : next_state <= x ? s0 : mon_x;
s0 : next_state <= x ? s0 : s1;
s1 : next_state <= x ? s2 : mon_x;
s2 : next_state <= y ? p1 : jug;
jug : next_state <= y ? p1 : p0;
p1 : next_state <= p1;
p0 : next_state <= p0;
default : next_state <= start;
endcase
end
assign f = (current_state == out_f);
assign g = (current_state == s2 || current_state == jug || current_state == p1);
endmodule
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