FPGA AD模块

XADC

XC7A15T

自带转换

The ADC conversion data is stored indedicated registers called status registers. These registers are accessible through the FPGA interconnect using a 16-bit synchronous read and write port called the dynamic

Analog-capable I/O have the ADxP or ADxN suffix on the I/O name in the package files.

Auxiliary analog inputs must be connected to the top level of the design.

The DRP is the interface between the XADC and FPGA. All XADC registers can be accessed from the FPGA logic using this interface. For more details on the timing for these DRP signals,

reconfiguration port (DRP).
conversion 转换
transition 转变，过渡
auxiliary 辅助 物
ferrite 铁素体
bead 珠子
commence 着手
diagram 图表
bank0
packagefile

To allow access to the status registers (measurement results) from the FPGA logic, the XADC must be instantiated