Android OrangePi 4G IOT(二) - MTK更换调试串口

原创 已于 2022-05-23 22:35:51 修改 · 3.5k 阅读 · 3
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#物联网 #iot
于 2022-05-14 20:50:36 首次发布

一、Debug LOG串口更改

orangepi 4G iot的默认的log调试串口是在板子后面的，使用起来不方便，之前UART0焊接不好导致焊盘弄坏了，没办法，准备修改成插针的40pin引脚的的UART1 （即使UTXD1和URXD1）      

本文就是将板子默认debug串口从UART0改成了UART1

40 pin串口UART1：

二：UART相关代码以及设置修改

修改PIN脚的工具

修改的地方可以参考以下代码

1: /home/ubuntu/Mediatek/code/vendor/mediatek/proprietary/bootable/bootloader/preloader/custom/bd6737m_35g_b_m0/cust_bldr.mak

###################################################################
# Include Project Feautre  (cust_bldr.h)
###################################################################

#ifeq ("$(MTK_EMMC_SUPPORT)","yes")
ifdef MTK_EMMC_SUPPORT
CFG_BOOT_DEV :=BOOTDEV_SDMMC
else
CFG_BOOT_DEV :=BOOTDEV_NAND
endif

CFG_UART_LOG :=UART2
CFG_UART_META :=UART2
#CFG_UART_LOG :=UART1 -> 20220515
#CFG_UART_META :=UART1

CFG_USB_UART_SWITCH := 0

2：/home/ubuntu/Mediatek/code/vendor/mediatek/proprietary/bootable/bootloader/preloader/platform/mt6735/default.mak

###################################################################
# Default Internal Feautre
###################################################################
HW_INIT_ONLY :=

###################################################################
# Default Project Feautre  (cust_bldr.h)
###################################################################

CFG_BOOT_DEV :=BOOTDEV_SDMMC

CFG_FPGA_PLATFORM :=0
# Setting for bring up, 
# booting from SRAM
CFG_BYPASS_EMI :=0
#Pull Hi Flash enable bit for UART META
CFG_ENABLE_GPIO_CHK_POINT_WITH_UART_META :=0

CFG_EVB_PLATFORM :=0
CFG_BATTERY_DETECT :=1
CFG_HIGH_BATTERY_VOLTAGE_SUPPORT :=0
CFG_UART_TOOL_HANDSHAKE :=1
CFG_USB_TOOL_HANDSHAKE :=1
CFG_USB_DOWNLOAD :=1
CFG_LOG_BAUDRATE :=921600
CFG_META_BAUDRATE :=115200
CFG_UART_LOG :=UART2
CFG_UART_META :=UART2
#CFG_UART_LOG :=UART1 ->20220515
#CFG_UART_META :=UART1

#only enable in eng mode
ifeq ("$(TARGET_BUILD_VARIANT)","eng")
CFG_OUTPUT_PL_LOG_TO_UART1:=0
CFG_FUNCTION_TRACER_SUPPORT :=0
else
CFG_OUTPUT_PL_LOG_TO_UART1:=0
CFG_FUNCTION_TRACER_SUPPORT :=0
endif

CFG_EMERGENCY_DL_SUPPORT :=1
CFG_EMERGENCY_DL_TIMEOUT_MS :=1000*5
CFG_EMERGENCY_MAX_TIMEOUT_MS :=1000*0x3fff
CFG_USBIF_COMPLIANCE :=0
CFG_MMC_ADDR_TRANS :=1
CFG_LEGACY_USB_DOWNLOAD :=0

CFG_USB_UART_SWITCH := 0

CFG_HW_WATCHDOG :=1
CFG_BOOT_ARGUMENT :=1
CFG_BOOT_ARGUMENT_BY_ATAG := 1
CFG_RAM_CONSOLE :=1
CFG_MTJTAG_SWITCH :=0
CFG_MDMETA_DETECT :=0
CFG_APWDT_DISABLE :=0
CFG_MDWDT_DISABLE :=0
CFG_SYS_STACK_SZ :=3*1024

CFG_WORLD_PHONE_SUPPORT :=1

KPD_USE_EXTEND_TYPE := 0
ONEKEY_REBOOT_NORMAL_MODE_PL :=1
KPD_PMIC_LPRST_TD :=1
MTK_PMIC_RST_KEY :=

CFG_USB_AUTO_DETECT :=0
CFG_USB_AUTO_DETECT_TIMEOUT_MS :=1000*3

CFG_FEATURE_ENCODE :=v1

FEATURE_DOWNLOAD_SCREEN :=0

MTK_EFUSE_WRITER_SUPPORT :=no

DIAG_COMPOSITE_PRELOADER :=0
CONFIG_MTK_USB_UNIQUE_SERIAL :=0
###################################################################
# image loading options
###################################################################

#For Normal Boot
CFG_LOAD_UBOOT :=1
#For Dummy AP
CFG_LOAD_MD_ROM :=0
CFG_LOAD_MD_RAMDISK :=0
CFG_LOAD_MD_DSP :=0
CFG_LOAD_MD3_ROM :=0
#For SLT and Dummy AP
CFG_LOAD_AP_ROM :=0

#For CTP
CFG_LOAD_CONN_SYS :=0
#For SLT
CFG_LOAD_SLT_MD :=0
CFG_LOAD_SLT_MD32 :=0

###################################################################
# Dummy Load address
# If image header have load address, we use address in image header
# If not, we use address here
###################################################################
#For Normal Boot
CFG_UBOOT_MEMADDR       :=0x41E00000
#For Dummy AP
CFG_MD1_ROM_MEMADDR     :=0x42000000
CFG_MD1_RAMDISK_MEMADDR :=0x49CC0000
CFG_MD2_ROM_MEMADDR     :=0x42000000
CFG_MD2_RAMDISK_MEMADDR :=0x43400000
CFG_MD_DSP_MEMADDR      :=0x4A000000
CFG_MD3_ROM_MEMADDR     :=0x52000000
#For SLT and Dummy AP
CFG_AP_ROM_MEMADDR      :=0x62000000
#For CTP
CFG_CONN_SYS_MEMADDR    :=0x45A00000
#For SLT
CFG_TDD_MD_ROM_MEMADDR   :=0x40000000
CFG_TDD_ONLY_ROM_MEMADDR :=0x41000000
CFG_FDD_MD_ROM_MEMADDR   :=0x42000000
CFG_2G_MD_ROM_MEMADDR    :=0x43000000
CFG_MD32P_ROM_MEMADDR    :=0x44000000
CFG_MD32D_ROM_MEMADDR    :=0x45002000
CFG_BOOTA64_MEMADDR 	 :=0x40000000
CFG_DTB_MEMADDR 	 :=0x40000300
CFG_IMAGE_AARCH64_MEMADDR :=0x40080000


#For ATF
CFG_ATF_ROM_MEMADDR   :=0x43001000-0x240
CFG_BOOTIMG_HEADER_MEMADDR	 :=0x40010800

CFG_ATF_SUPPORT :=1
CFG_ATF_LOG_SUPPORT :=1
CFG_TEE_SUPPORT :=0
CFG_MICROTRUST_TEE_SUPPORT :=0
CFG_TRUSTONIC_TEE_SUPPORT :=0
CFG_TEE_SECURE_MEM_PROTECTED :=1
CFG_TEE_TRUSTED_APP_HEAP_SIZE := 0xA00000
CFG_GOOGLE_TRUSTY_SUPPORT :=0

#For SRAM Protection
CFG_NON_SECURE_SRAM_ADDR :=0x0010DC00
CFG_NON_SECURE_SRAM_SIZE :=0x4000

3: /home/ubuntu/Mediatek/code/trusty/vendor/mediatek/proprietary/platform/mt6735/rules.mk

# 
# Copyright (C) 2015 MediaTek Inc. 
#
# Modification based on code covered by the below mentioned copyright
# and/or permission notice(S). 
#

#
# Copyright (c) 2015, Google, Inc. All rights reserved
#
# Permission is hereby granted, free of charge, to any person obtaining
# a copy of this software and associated documentation files
# (the "Software"), to deal in the Software without restriction,
# including without limitation the rights to use, copy, modify, merge,
# publish, distribute, sublicense, and/or sell copies of the Software,
# and to permit persons to whom the Software is furnished to do so,
# subject to the following conditions:
#
# The above copyright notice and this permission notice shall be
# included in all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
# IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
# CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
# TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#

LOCAL_DIR := $(GET_LOCAL_DIR)

MODULE := $(LOCAL_DIR)

ifeq (false,$(call TOBOOL,$(KERNEL_32BIT)))
ARCH := arm64
else
ARCH := arm
ARM_CPU := cortex-a15
endif
WITH_SMP := 1

KERNEL_BASE ?= 0x4f040000
MEMBASE ?= $(KERNEL_BASE)
MEM_SIZE ?= 0x200000

ifeq (false,$(call TOBOOL,$(KERNEL_32BIT)))
MEMSIZE ?= 1
else
MEMSIZE ?= $(MEM_SIZE)
endif
CFG_LOG_REG_BASE ?= UART1_BASE
#CFG_LOG_REG_BASE ?= UART0_BASE -> 20220515
CFG_LOG_BAUDRATE ?= 921600

GLOBAL_INCLUDES += \
	$(LOCAL_DIR)/include

MODULE_SRCS += \
	$(LOCAL_DIR)/debug.c \
	$(LOCAL_DIR)/platform.c \
	$(LOCAL_DIR)/smc.c \
	$(LOCAL_DIR)/uart.c \
	$(LOCAL_DIR)/gpt.c \
	$(LOCAL_DIR)/reg_base.c \

MODULE_DEPS += \
	dev/interrupt/arm_gic \
	dev/timer/arm_generic

GLOBAL_DEFINES += \
	MEMBASE=$(MEMBASE) \
	MEMSIZE=$(MEMSIZE) \
	MMU_WITH_TRAMPOLINE=1 \

ifeq (false,$(call TOBOOL,$(KERNEL_32BIT)))
else
GLOBAL_DEFINES += \
	WITH_TIMERS_MIGRATION=1 \
	UART_LOG_BAUDRATE=$(CFG_LOG_BAUDRATE) \
	UART_LOG_REG_BASE=$(CFG_LOG_REG_BASE) \
	DISABLE_TRACE_INIT_AFTER_BOOTUP=1 \

ifeq (eng,$(TARGET_BUILD_VARIANT))
GLOBAL_DEFINES += \
	WITH_MT_TRUSTY_DEBUGFS=1 \
	WITH_HWCRYPTO_UNITTEST=1
endif # TARGET_BUILD_VARIANT
endif # KERNEL_32BIT==true

LINKER_SCRIPT += \
	$(BUILDDIR)/system-onesegment.ld

include make/module.mk

4：/home/ubuntu/Mediatek/code/vendor/mediatek/proprietary/bootable/bootloader/preloader/platform/mt6735/mode/DUMMY_AP.mak

HW_INIT_ONLY :=
CFG_LOAD_MD_ROM :=1
CFG_LOAD_MD_RAMDISK :=1
CFG_LOAD_AP_ROM :=1
CFG_LOAD_UBOOT :=0
CFG_LOAD_MD_DSP :=1
CFG_LOAD_MD3_ROM :=1
CFG_ATF_SUPPORT :=0
CFG_UART_LOG :=UART2
CFG_UART_META :=UART2

5：/home/ubuntu/Mediatek/code/vendor/mediatek/proprietary/bootable/bootloader/lk/platform/mt6735/uart.c

void uart_init_early(void)
{
	// 20220521
	#ifdef GPIO_UART_UTXD0_PIN
    mt_set_gpio_mode(GPIO_UART_UTXD0_PIN, GPIO_UART_UTXD0_PIN_M_UTXD);
    mt_set_gpio_dir(GPIO_UART_UTXD0_PIN, GPIO_DIR_OUT);
    #endif

    #ifdef GPIO_UART_URXD0_PIN
    mt_set_gpio_mode(GPIO_UART_URXD0_PIN, GPIO_UART_URXD0_PIN_M_URXD);
    mt_set_gpio_dir(GPIO_UART_URXD0_PIN, GPIO_DIR_IN);
    mt_set_gpio_pull_enable(GPIO_UART_URXD0_PIN, GPIO_PULL_ENABLE);
    mt_set_gpio_pull_select(GPIO_UART_URXD0_PIN, GPIO_PULL_UP); 
    #endif

    #ifdef GPIO_UART_UTXD1_PIN
    mt_set_gpio_mode(GPIO_UART_UTXD1_PIN, GPIO_UART_UTXD1_PIN_M_UTXD);
    mt_set_gpio_dir(GPIO_UART_UTXD1_PIN, GPIO_DIR_OUT);
    #endif

    #ifdef GPIO_UART_URXD1_PIN
    mt_set_gpio_mode(GPIO_UART_URXD1_PIN, GPIO_UART_URXD1_PIN_M_URXD);
    mt_set_gpio_dir(GPIO_UART_URXD1_PIN, GPIO_DIR_IN);
    mt_set_gpio_pull_enable(GPIO_UART_URXD1_PIN, GPIO_PULL_ENABLE);
    mt_set_gpio_pull_select(GPIO_UART_URXD1_PIN, GPIO_PULL_UP); 
    #endif
    
    #ifdef GPIO_UART_UTXD2_PIN
    mt_set_gpio_mode(GPIO_UART_UTXD2_PIN, GPIO_UART_UTXD2_PIN_M_UTXD);
    mt_set_gpio_dir(GPIO_UART_UTXD2_PIN, GPIO_DIR_OUT);
    #endif

    #ifdef GPIO_UART_URXD2_PIN
    mt_set_gpio_mode(GPIO_UART_URXD2_PIN, GPIO_UART_URXD2_PIN_M_URXD);
    mt_set_gpio_dir(GPIO_UART_URXD2_PIN, GPIO_DIR_IN);
    mt_set_gpio_pull_enable(GPIO_UART_URXD2_PIN, GPIO_PULL_ENABLE);
    mt_set_gpio_pull_select(GPIO_UART_URXD2_PIN, GPIO_PULL_UP); 
    #endif
    
    #ifdef GPIO_UART_UTXD3_PIN
    mt_set_gpio_mode(GPIO_UART_UTXD3_PIN, GPIO_UART_UTXD3_PIN_M_UTXD);
    mt_set_gpio_dir(GPIO_UART_UTXD3_PIN, GPIO_DIR_OUT);
    #endif

    #ifdef GPIO_UART_URXD3_PIN
    mt_set_gpio_mode(GPIO_UART_URXD3_PIN, GPIO_UART_URXD3_PIN_M_URXD);
    mt_set_gpio_dir(GPIO_UART_URXD3_PIN, GPIO_DIR_IN);
    mt_set_gpio_pull_enable(GPIO_UART_URXD3_PIN, GPIO_PULL_ENABLE);
    mt_set_gpio_pull_select(GPIO_UART_URXD3_PIN, GPIO_PULL_UP); 
    #endif


	#ifdef __ENABLE_UART_LOG_SWITCH_FEATURE__
	if(get_uart_port_id() == 1){
		mtk_set_current_uart(UART1);
		mtk_uart_power_on(UART1);
	}else if(get_uart_port_id() == 2){
		mtk_set_current_uart(UART2);
		mtk_uart_power_on(UART2);
	}else if(get_uart_port_id() == 3){
		mtk_set_current_uart(UART3);
		mtk_uart_power_on(UART3);
	}else if(get_uart_port_id() == 4){
		mtk_set_current_uart(UART4);
		mtk_uart_power_on(UART4);
	}
#ifndef CONFIG_DENALI_2
	else if(get_uart_port_id() == 5){
		mtk_set_current_uart(UART5);
		mtk_uart_power_on(UART5);
	}
#endif
	else {
		mtk_set_current_uart(UART4);
		mtk_uart_power_on(UART4);
	}
	#else
	mtk_set_current_uart(UART1);
	mtk_uart_power_on(UART1);
	#endif

	DRV_SetReg32(UART_FCR(g_uart), UART_FCR_FIFO_INIT); /* clear fifo */
	mt65xx_reg_sync_writew(UART_NONE_PARITY | UART_WLS_8 | UART_1_STOP, UART_LCR(g_uart));
	g_brg = CONFIG_BAUDRATE;
	uart_setbrg();
}

6：/home/ubuntu/Mediatek/code/orangepi/projects/IoT/IoT_mt6737m/IoT_bd6737m_35g_b_m0_op_smt_hd720_pcb_v2/code/kernel-3.18/arch/arm/boot/dts/mt6735m.dtsi

	/* chosen */
		chosen {
			bootargs = "console=tty0 console=ttyMT1,921600n1 root=/dev/ram \
			initrd=0x44000000,0x1000000 loglevel=8 androidboot.hardware=mt6735";
		};

7：/home/ubuntu/Mediatek/code/orangepi/projects/IoT/IoT_mt6737m/IoT_bd6737m_35g_b_m0_op_smt_hd720_pcb_v2/code/kernel-3.18/arch/arm/configs/bd6737m_35g_b_m0_debug_defconfig

#
# Boot options
#
CONFIG_USE_OF=y
CONFIG_ATAGS=y
# CONFIG_DEPRECATED_PARAM_STRUCT is not set
CONFIG_BUILD_ARM_APPENDED_DTB_IMAGE=y
CONFIG_BUILD_ARM_APPENDED_DTB_IMAGE_NAMES="bd6737m_35g_b_m0"
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZBOOT_ROM_BSS=0
# CONFIG_ARM_APPENDED_DTB is not set
CONFIG_CMDLINE="console=tty0 console=ttyMT1,921600n1 root=/dev/ram vmalloc=496M slub_max_order=0 slub_debug=O "
CONFIG_CMDLINE_FROM_BOOTLOADER=y
# CONFIG_CMDLINE_EXTEND is not set
# CONFIG_CMDLINE_FORCE is not set
# CONFIG_XIP_KERNEL is not set
# CONFIG_KEXEC is not set
# CONFIG_CRASH_DUMP is not set
CONFIG_AUTO_ZRELADDR=y


三、烧录Android Image

拔掉跳线冒J5，运行sudo ./flash_tool，打开Flash Tool，找到对应的scatter文件，先选择firmware upgrade，然后点击Download 按钮，然后插上micro usb线，就可以下载Android镜像进行烧录了。

拔掉USB烧录线，然后按下powerkey开启电源

[PLFM] USB cable in
[pmic_IsUsbCableIn] 1
[pmic_IsUsbCableIn] 1
pl pmic powerkey Release
[pmic_IsUsbCableIn] 1
pl pmic powerkey Release
[pmic_IsUsbCableIn] 1
pl pmic powerkey Release
[pmic_IsUsbCableIn] 1
pl pmic powerkey Release
[pmic_IsUsbCableIn] 1
pl pmic powerkey Release
[pmic_IsUsbCableIn] 1
pl pmic powerkey Press
[LIB] NS-CHIP
GCPU Enhance,V1.0
[TZ_INIT] tee_verify_image : passed
[BLDR] bldr load tee part ret=0x0, addr=0x43001000
[BLDR] part_load_raw_part ret=0x0
[BLDR] part_load_images ret=0x0
ignore bat check

[PLFM] boot to LK by ATAG.
boot reason: 1
boot mode: 0
META COM0: 0
boot uart: 0x11003000
boot uart_baudrate: 921600
boot uart_enable: 1
rank[0] size: 0x3FFC0000
tee reserved mem: 0x000000007FFC0000, 0x0000000000040000
md_type[0]: 0x0
md_type[1]: 0x0
boot time: 8540
DDR reserve mode: enable = 0, success = 0
dram buffer size: 1688768
SMC: 0x0
LK: 0x6
KERNEL: 0x6
NONSEC SRAM Addr: 0x10DC00
NONSEC SRAM Size: 0x4000
DTB Addr: 0x0
DTB Size: 0x0
PL_VERSION = 0.1.00
[TZ_INIT] atf_log_port : 0x11003000
[TZ_INIT] atf_log_baudrate : 0xE1000
[TZ_INIT] atf_irq_num : 281
[TZ_INIT] ATF log buffer start : 0x7FFC0000
[TZ_INIT] ATF log buffer size : 0x40000
[TZ_INIT] ATF aee buffer start : 0x7FFFC000
[TZ_INIT] ATF aee buffer size : 0x4000
[BLDR] Others, jump to ATF

[BLDR] jump to 0x41E00000
[BLDR] <0x41E00000>=0xEA000007
[BLDR] <0x41E00004>=0xEA007460
[TZ_SEC_CFG] SRAMROM Secure Addr 0xDC00
[TZ_SEC_CFG] SRAMROM Secure Control 0x0
[TZ_SEC_CFG] SRAMROM Secure Control 0xB69
[TZ_SEC_CFG] SRAMROM Secure Control 0x1B680B69
[TZ_INIT] ATF entry addr, aligned addr : 0x43001000, 0x43000000
[TZ_EMI_MPU] MPU [0x43000000-0x4302FFFF]
[TZ_INIT] set secure memory protection : 0x43000000, 0x4302FFFF (1)
[TZ_INIT] Jump to ATF, then 0x41E00000
[ATF][     0.000000]BL33 boot argument location=0x4219c480
[ATF][     0.000000]BL33 boot argument size=0x170
[ATF][     0.000000]BL33 start addr=0x41e00000
[ATF][     0.000000]teearg addr=0x101000
[ATF][     0.000000]atf_magic=0x4d415446
[ATF][     0.000000]tee_support=0x0
[ATF][     0.000000]tee_entry=0x0
[ATF][     0.000000]tee_boot_arg_addr=0x101100
[ATF][     0.000000]atf_log_port=0x11003000
[ATF][     0.000000]atf_log_baudrate=0xe1000
[ATF][     0.000000]atf_log_buf_start=0x7ffc0000
[ATF][     0.000000]atf_log_buf_size=0x40000
[ATF][     0.000000]atf_aee_debug_buf_start=0x7fffc000
[ATF][     0.000000]atf_aee_debug_buf_size=0x4000
[ATF][     0.000000]atf_irq_num=281
[ATF][     0.000000]BL33_START_ADDRESS=0x41e00000
[ATF][     0.000000]atf chip_code[335]
[ATF][     0.000000]atf chip_ver[0]
[ATF][     0.000000]###@@@ MP0_MISC_CONFIG3:0x00000000 @@@###
[ATF][     0.000000]###@@@ MP0_MISC_CONFIG3:0x0000e000 @@@###
[ATF][     0.000000]mmap atf buffer : 0x7ffc0000, 0x40000
[ATF][     0.000000]mmap atf buffer (force 2MB aligned): 0x7fe00000, 0x200000
NOTICE:  BL3-1: v1.0(debug):
NOTICE:  BL3-1: Built : 18:10:55, May 21 2022
[ATF][     0.000000]sta=0x0 int=0xffc
[ATF][     0.000000]is_power_on_boot: true
[ATF][     0.000000]mt_log_setup - atf_buf_addr : 0x7ffc0100
[ATF][     0.000000]mt_log_setup - atf_buf_size : 0x2bf00
[ATF][     0.000000]mt_log_setup - atf_write_pos : 0x7ffc0100
[ATF][     0.000000]mt_log_setup - atf_read_pos : 0x7ffc0100
[ATF][     0.000000]mt_log_setup - atf_buf_lock : 0x0
[ATF][     0.000000]mt_log_setup - mt_log_buf_end : 0x7ffebfff
[ATF][     0.000000]mt_log_setup - ATF_CRASH_LAST_LOG_SIZE : 0x8000
[ATF][     0.000000]mt_log_setup - ATF_EXCEPT_BUF_SIZE_PER_CPU : 0x1000
[ATF][     0.000000]mt_log_setup - ATF_EXCEPT_BUF_SIZE : 0x8000
[ATF][     0.000000]mt_log_setup - PLATFORM_CORE_COUNT : 0x8
[ATF][     0.000000]mt_log_setup - atf_except_write_pos_per_cpu[0]: 0x7fff4000
[ATF][     0.000000]mt_log_setup - atf_except_write_pos_per_cpu[1]: 0x7fff5000
[ATF][     0.000000]mt_log_setup - atf_except_write_pos_per_cpu[2]: 0x7fff6000
[ATF][     0.000000]mt_log_setup - atf_except_write_pos_per_cpu[3]: 0x7fff7000
[ATF][     0.000000]mt_log_setup - atf_except_write_pos_per_cpu[4]: 0x7fff8000
[ATF][     0.000000]mt_log_setup - atf_except_write_pos_per_cpu[5]: 0x7fff9000
[ATF][     0.000000]mt_log_setup - atf_except_write_pos_per_cpu[6]: 0x7fffa000
[ATF][     0.000000]mt_log_setup - atf_except_write_pos_per_cpu[7]: 0x7fffb000
[ATF][     0.000000]mt_log_setup - atf_crash_flag : 0x0
[ATF][     0.000000]mt_log_setup - atf_crash_log_addr : 0x0
[ATF][     0.000000]mt_log_setup - atf_crash_log_size : 0x0
[ATF][     0.000000]ATF log service is registered (0x7ffc0000, aee:0x7fffc000)
[ATF][     0.000000]BL3-1: v1.0(debug):
[ATF][     0.000000]BL3-1: Built : 18:10:55, May 21 2022
INFO:    BL3-1: Initializing runtime services
[ATF][     0.000000][BL31] Jump to FIQD for initialization!
INFO:    BL3-1: Preparing for EL3 exit to normal world, LK
INFO:    BL3-1: Next image address = 0x41e00000
INFO:    BL3-1: Next image spsr = 0x1d3
[ATF][     0.000000][BL31] Final dump!
[0] [WDT]  mtk_wdt_mode LK config  mode value=5d
[0] [WDT]  mtk_wdt_mode_config LK  mode value=10, tmp:22000010
[0] [WDT] UB wdt init
[0] [WDT]  mtk_wdt_mode LK config  mode value=10
[0] [WDT]  mtk_wdt_mode_config LK  mode value=5d, tmp:2200005d
[0] WDT NONRST=0x20000000
[0] [PROFILE] ------- WDT Init  takes 3 ms --------
[0] [pmic_init] LK Start..................
[0] [pmic_init] MT6325 CHIP Code = 0x2820
[0] [pmic_init] Done
[0] [PROFILE] ------- pmic_init takes 1 ms --------
[0] [PROFILE] ------- platform_early_init takes 8 ms --------
[0] welcome to lk

[0] calling constructors
[0] initializing heap
[0] base 0x41e7c694 size 8927596 bytes
[0] initializing threads
[0] initializing dpc
[0] initializing timers
[0] creating bootstrap completion thread
[10] top of bootstrap2()
[20] initializing platform
[20]  ==LK info ==
[20]  Build time:May 21 2022, 18:27:19
[20]  chip_code[0x335]
[20]  chip_ver[0x0]
[20]  ==LK info ==
[20] platform_init()
[20] [mmc_init]: msdc0 start mmc_init_host() in LK...
[20] [msdc_init]: msdc0 Host controller intialization start
[20] [MSDC] config VEMC to 3V in lk
[20] [SD0] Pins mode(1), none(0), down(1), up(2), keep(3)
[20] [SD0] Pins mode(2), none(0), down(1), up(2), keep(3)
[20] [MSDC] config VEMC to 3V in lk
[20] [info][msdc_set_startbit 1248] read data start bit at rising edge
[20] [info][msdc_config_clksrc] input clock is 400000kHz
[20] [SD0] Bus Width: 1
[20] [info][msdc_config_clksrc] input clock is 400000kHz
[20] [info][msdc_set_startbit 1248] read data start bit at rising edge
[20] [SD0] SET_CLK(260kHz): SCLK(259kHz) MODE(0) DDR(0) DIV(385) DS(0) RS(0)
[20] [msdc_init]: msdc0 Host controller intialization done
[40] [mmc_init]: msdc0 start mmc_init_card()in LK...
[40] [mmc_init_card]: start
[140] [info][msdc_config_clksrc] input clock is 400000kHz
[140] [info][msdc_set_startbit 1248] read data start bit at rising edge
[140] [SD0] SET_CLK(260kHz): SCLK(259kHz) MODE(0) DDR(0) DIV(385) DS(0) RS(0)
[160] [SD0] Bus Width: 8
[160] [SD0] Switch to High-Speed mode!
[160] [SD0] Size: 7456 MB, Max.Speed: 52000 kHz, blklen(512), nblks(15269888), ro(0)
[160] [mmc_init_mem_card 3240][SD0] Initialized, eMMC50
[160] before host->cur_bus_clk(259740)
[160] [info][msdc_config_clksrc] input clock is 400000kHz
[160] [info][msdc_set_startbit 1248] read data start bit at rising edge
[180] [SD0] SET_CLK(52000kHz): SCLK(50000kHz) MODE(0) DDR(0) DIV(2) DS(0) RS(0)
[180] host->cur_bus_clk(50000000)
[180] [mmc_init_card]: finish successfully
[180] [mt_part_register_device]
[180] [GPT_LK]Parsing Primary GPT now...
[180] [GPT_LK][0]name=proinfo, part_id=8, start_sect=0x400, nr_sects=0x1800
[180] [GPT_LK][1]name=nvram, part_id=8, start_sect=0x1c00, nr_sects=0x2800
[180] [GPT_LK][2]name=protect1, part_id=8, start_sect=0x4400, nr_sects=0x5000
[180] [GPT_LK][3]name=protect2, part_id=8, start_sect=0x9400, nr_sects=0x5000
[180] [GPT_LK][4]name=lk, part_id=8, start_sect=0xe400, nr_sects=0x400
[180] [GPT_LK][5]name=para, part_id=8, start_sect=0xe800, nr_sects=0x400
[180] [GPT_LK][6]name=boot, part_id=8, start_sect=0xec00, nr_sects=0x8000
[200] [GPT_LK][7]name=recovery, part_id=8, start_sect=0x16c00, nr_sects=0x8000
[200] [GPT_LK][8]name=logo, part_id=8, start_sect=0x1ec00, nr_sects=0x4000
[200] [GPT_LK][9]name=expdb, part_id=8, start_sect=0x22c00, nr_sects=0x5000
[200] [GPT_LK][10]name=seccfg, part_id=8, start_sect=0x27c00, nr_sects=0x400
[200] [GPT_LK][11]name=oemkeystore, part_id=8, start_sect=0x28000, nr_sects=0x1000
[200] [GPT_LK][12]name=secro, part_id=8, start_sect=0x29000, nr_sects=0x3000
[200] [GPT_LK][13]name=keystore, part_id=8, start_sect=0x2c000, nr_sects=0x4000
[200] [GPT_LK][14]name=tee1, part_id=8, start_sect=0x30000, nr_sects=0x2800
[200] [GPT_LK][15]name=tee2, part_id=8, start_sect=0x32800, nr_sects=0x2800
[200] [GPT_LK][16]name=frp, part_id=8, start_sect=0x35000, nr_sects=0x800
[200] [GPT_LK][17]name=nvdata, part_id=8, start_sect=0x35800, nr_sects=0x10000
[200] [GPT_LK][18]name=metadata, part_id=8, start_sect=0x45800, nr_sects=0x12800
[220] [GPT_LK][19]name=system, part_id=8, start_sect=0x58000, nr_sects=0x300000
[220] [GPT_LK][20]name=cache, part_id=8, start_sect=0x358000, nr_sects=0xc8000
[220] [GPT_LK][21]name=userdata, part_id=8, start_sect=0x420000, nr_sects=0xa67c00
[220] [GPT_LK][22]name=flashinfo, part_id=8, start_sect=0xe87c00, nr_sects=0x8000
[220] [GPT_LK]Success to find valid GPT.
[220] [SD0] boot device found
[220] [PROFILE] ------- NAND/EMMC init takes 104 ms --------
[220] [PART_LK][get_part] boot
[220] [LK_BOOT] Load '<null>' partition to 0x45000000 (608 bytes in 1 ms)
[220] [PART_LK][get_part] boot
[540] [LK_BOOT] Load '<null>' partition to 0x45000000 (7256064 bytes in 159 ms)
[540] Kernel(0) zimage_addr:0x45000800(6dadb8),dtb_addr:0x456db5b8(fb2a)
[540] Copy DTB from 0x456db5b8 to 0x4e000000(fb2a)
[540] [LK] fdt setup addr:0x4e000000 status:1!!!
[540] [LEDS]LK: leds_init: mt65xx_backlight_off
[540] [LEDS]LK: mt65xx_backlight_off
[540] [LEDS]LK: lcd-backlight level is 0
[540] [LK_DDP/INFO]enable       pwm0  clk, CG0 0xffffffff, CG1 0xfffffffc, dummy CON = 0x0
[540] [LK_DDP/PWM][PWM] set reg[0x102100b0] = 0x00000000
[540] [LK_DDP/PWM][PWM] disp_pwm_init : CLK_CFG_7 0x0 => 0x0
[560] [LK_DDP/PWM][PWM] disp_pwm_init : PWM config data (0,0)
[560] [LK_DDP/PWM][PWM] set reg[0x1100e010] = 0x00000000
[560] [LK_DDP/PWM][PWM] set reg[0x1100e014] = 0x000003ff
[560] [LK_DDP/PWM][PWM] disp_pwm_set_backlight(id = 0x1, level_1024 = 0)
[560] [LK_DDP/PWM][PWM] set reg[0x1100e008] = 0x00000000
[560] [LK_DDP/PWM][PWM] set reg[0x1100e014] = 0x000003ff
[560] [LK_DDP/PWM][PWM] set reg[0x1100e000] = 0x00000000
[560] [LK_DDP/PWM][PWM] set reg[0x1100e008] = 0x00000001
[560] [LK_DDP/PWM][PWM] set reg[0x1100e008] = 0x00000000
[560] [LK_DDP/PWM][PWM] reg[0x1100e000] = 0x00000000
[560] [LK_DDP/PWM][PWM] reg[0x1100e004] = 0x00000000
[560] [LK_DDP/PWM][PWM] reg[0x1100e008] = 0x00000000
[560] [LK_DDP/PWM][PWM] reg[0x1100e00c] = 0x00000000
[560] [LK_DDP/PWM][PWM] reg[0x1100e010] = 0x00000000
[560] [LK_DDP/PWM][PWM] reg[0x1100e014] = 0x00000000
[560] [LK_DDP/PWM][PWM] reg[0x1100e018] = 0x00000000
[580] [LK_DDP/PWM][PWM] reg[0x1100e01c] = 0x00000000
[580] [LK_DDP/PWM][PWM] reg[0x1100e020] = 0x00000000
[580] [LK_DDP/PWM][PWM] reg[0x1100e024] = 0x00000000
[580] [LK_DDP/PWM][PWM] reg[0x1100e028] = 0x00000000
[580] [PROFILE] ------- led init takes 16 ms --------
[580] [upmu_is_chr_det] 1
[580] [PART_LK][get_part] para
[LK_ENV]ENV SIG Wrong
[LK_ENV]no valid env
[580] [PROFILE] ------- ENV init takes 2 ms --------
[580] [DISP]func|disp_lcm_probe
[580] [DISP]we will check lcm: ili9881c_hd720_dsi_vdo_cpt
[580] [DISP]func|_display_interface_path_init
[580] [LK_DDP/ddp_manager]scenario display_interface acquire mutex 0 , left mutex 0x1e!
[580] [LK_DDP/ddp_manager]assign default irqs table index 0
[580] [LK_DDP/ddp_manager]create handle 0x41e69f40 on scenario display_interface
[600] [LK_DDP/ddp_manager] scenario display_interface include module ovl0
[600] [LK_DDP/ddp_manager] scenario display_interface include module color0
[600] [LK_DDP/ddp_manager] scenario display_interface include module ccorr
[600] [LK_DDP/ddp_manager] scenario display_interface include module aal
[600] [LK_DDP/ddp_manager] scenario display_interface include module gamma
[600] [LK_DDP/ddp_manager] scenario display_interface include module dither
[600] [LK_DDP/ddp_manager] scenario display_interface include module rdma0
[600] [LK_DDP/ddp_manager] scenario display_interface include module pwm0
[600] [LK_DDP/ddp_manager] scenario display_interface include module dsi0
[600] [DISPCHECK]dpmgr create path SUCCESS(0x41e69f40)
[600] [LK_DDP/ddp_manager]set dst module on scenario display_interface, module dsi0
[600] [LK_DDP/ddp_path]ddp_set_dst_module, scenario=display_interface, dst_module=dsi0
[620] [LK_DDP/ddp_path]dsi0  is already on path
[620] [DISPCHECK]dpmgr set dst module FINISHED(dsi0 )
[620] [LK_DDP/ddp_manager]path set lcm drv handle 0x41e69f40
[620] [LK_DDP/ddp_manager]dsi0  set lcm utils
[620] [LK_DDP/ddp_manager]path init on scenario display_interface
[620] [LK_DDP/ddp_path]ddp path m4u off
[620] [LK_DDP/ddp_path]ddp path top clock on
[620] [LK_DDP/INFO]enable       smi  clk, CG0 0xfffffffc, CG1 0xfffffffc, dummy CON = 0xfffffffc
[620] [LK_DDP/INFO]enable       mutex  clk, CG0 0xfffffffc, CG1 0xfffffffc, dummy CON = 0xfffffffc
[620] [LK_DDP/ddp_path]ddp CG:fffffffc
[620] [LK_DDP/ddp_path]mutex sof: dsi0 dst module dsi0 :vido_mode
[620] [LK_DDP/ddp_path]module ovl0  added to mutex 0
[620] [LK_DDP/ddp_path]module color0  added to mutex 0
[620] [LK_DDP/ddp_path]module ccorr added to mutex 0
[620] [LK_DDP/ddp_path]module aal  added to mutex 0
[640] [LK_DDP/ddp_path]module gamma  added to mutex 0
[640] [LK_DDP/ddp_path]module dither added to mutex 0
[640] [LK_DDP/ddp_path]module rdma0  added to mutex 0
[640] [LK_DDP/ddp_path]module pwm0  added to mutex 0
[640] [LK_DDP/ddp_path]mutex 0 value=0x2f940, sof=dsi0
[640] [LK_DDP/ddp_path]path connect on scenario display_interface
[640] [LK_DDP/ddp_path]connect_path: ovl0  to dsi0
[640] [LK_DDP/ddp_path]connect mout ovl0  to color0   value 0x1
[640] [LK_DDP/ddp_path]connect mout dither to rdma0   value 0x1
[640] [LK_DDP/ddp_path]connect out_s rdma0  to dsi0 , bits=0x2
[640] [LK_DDP/ddp_path]connect in_s ovl0  to color0 , bits=0x1
[640] [LK_DDP/ddp_path]connect in_s rdma0  to dsi0 , bits=0x1
[640] [LK_DDP/ddp_manager]scenario display_interface init module  ovl0
[640] [LK_DDP/INFO]enable       ovl0  clk, CG0 0xfffffbfc, CG1 0xfffffffc, dummy CON = 0xfffffbfc
[640] [LK_DDP/OVL]OVL0Init open CG 0xfffffbfc
[660] [LK_DDP/ddp_manager]scenario display_interface init module  color0
[660] [LK_DDP/INFO]enable       color0  clk, CG0 0xffffbbfc, CG1 0xfffffffc, dummy CON = 0xffffbbfc
[660] [LK_DDP/ddp_manager]scenario display_interface init module  aal
[660] [LK_DDP/INFO]enable       aal  clk, CG0 0xfffebbfc, CG1 0xfffffffc, dummy CON = 0xfffebbfc
[660] [LK_DDP/ddp_manager]scenario display_interface init module  gamma
[660] [LK_DDP/INFO]enable       gamma  clk, CG0 0xfffcbbfc, CG1 0xfffffffc, dummy CON = 0xfffcbbfc
[660] [LK_DDP/ddp_manager]scenario display_interface init module  rdma0
[660] [LK_DDP/INFO]enable       rdma0  clk, CG0 0xfffcb3fc, CG1 0xfffffffc, dummy CON = 0xfffcb3fc
[660] [LK_DDP/RDMA]RDMA0Init CG 0xfffcb3fc
[660] [LK_DDP/ddp_manager]scenario display_interface init module  dsi0
[660] [DISP]func|ddp_dsi_init
[660] [LK_DDP/INFO]enable       dsi0  clk, CG0 0xfffcb3fc, CG1 0xfffffff0, dummy CON = 0xfffcb3fc
[670] [DISPCHECK]dsi0 init finished
[680] [LK_DDP/ddp_manager]path config ovl 0, rdma 0, wdma 0, dst 1 on handle 0x41e69f40 scenario display_interface
[680] [LK_DDP/ddp_manager]scenario display_interface  config module ovl0
[680] [LK_DDP/ddp_manager]scenario display_interface  config module color0
[680] [LK_DDP/ddp_manager]scenario display_interface  config module aal
[680] [LK_DDP/ddp_manager]scenario display_interface  config module gamma
[680] [LK_DDP/ddp_manager]scenario display_interface  config module dither
[680] [LK_DDP/DITHER]error:[DITHER] invalid dither bpp = 0
[680] [LK_DDP/ddp_manager]scenario display_interface  config module rdma0
[680] [LK_DDP/RDMA]FIFO_VALID_Size      = 0x020 = 32
[680] [LK_DDP/RDMA]ultra_low_level      = 0x06b = 107
[680] [LK_DDP/RDMA]pre_ultra_low_level  = 0x05f = 95
[680] [LK_DDP/RDMA]pre_ultra_high_level = 0x06b = 107
[680] [LK_DDP/RDMA]ultra_high_ofs       = 0x001 = 1
[700] [LK_DDP/RDMA]pre_ultra_low_ofs    = 0x0a0 = 160
[700] [LK_DDP/RDMA]pre_ultra_high_ofs   = 0x001 = 1
[700] [LK_DDP/ddp_manager]scenario display_interface  config module dsi0
[700] [DISP]func|ddp_dsi_config
[700] [DISPCHECK][DDPDSI] DSI Mode: BURST_VDO_MODE
[700] [DISPCHECK][DDPDSI] LANE_NUM: 4,data_format: 0,vertical_sync_active: 0
[700] [DISPCHECK][DDPDSI] vact: 8, vbp: 16, vfp: 16, vact_line: 1280, hact: 10, hbp: 80, hfp: 80, hblank: 0
[700] [DISPCHECK][DDPDSI] pll_select: 0, pll_div1: 0, pll_div2: 0, fbk_div: 0,fbk_sel: 0, rg_bir: 0
[700] [DISPCHECK][DDPDSI] rg_bic: 0, rg_bp: 0, PLL_CLOCK: 250, dsi_clock: 0, ssc_range: 0,      ssc_disable: 0, compatibility_for_nvk: 0, cont_clock: 0
[700] [DISPCHECK][DDPDSI] lcm_ext_te_enable: 0, noncont_clock: 0, noncont_clock_period: 0
[700] [DISP]func|DSI_PHY_clk_setting
[700] [DISP][mipitx/reg]0x14018044=0x88492481
[700] [DISP][mipitx/reg]0x14018044=0x88492483
[720] [DISP][mipitx/reg]0x14018040=0x00000082
[720] [DISP][mipitx/reg]0x14018000=0x00000402
[720] [DISP][mipitx/reg]0x14018000=0x00000403
[720] [DISP][mipitx/reg]0x14018068=0x00000003
[720] [DISP][mipitx/reg]0x14018068=0x00000101
[720] [DISP][mipitx/reg]0x14018050=0x00000000
[720] [DISP][mipitx/reg]0x14018050=0x00000000
[720] [DISP][mipitx/reg]0x14018050=0x00000000
[720] [DISP][mipitx/reg]0x14018054=0x00000003
[720] [DISP][mipitx/reg]0x14018058=0x26000000
[720] [DISP][mipitx/reg]0x14018058=0x26760000
[720] [DISP][mipitx/reg]0x14018058=0x26762700
[720] [DISP][mipitx/reg]0x14018058=0x26762762
[720] [DISP][mipitx/reg]0x14018054=0x00000003
[720] [DISP][mipitx/reg]0x14018054=0x01b10003
[720] [DISP][mipitx/reg]0x1401805c=0x048b0000
[720] [DISP][mipitx/reg]0x1401805c=0x048b048b
[720] [DISP][dsi_drv.c] PLL config:data_rate=500,txdiv=1,pcw=645277538,delta1=5,pdelta1=0x48b
[720] [DISP][mipitx/reg]0x14018054=0x01b10007
[740] [DISP][mipitx/reg]0x14018004=0x00000821
[740] [DISP][mipitx/reg]0x14018008=0x00000401
[740] [DISP][mipitx/reg]0x1401800c=0x00000101
[740] [DISP][mipitx/reg]0x14018010=0x00000101
[740] [DISP][mipitx/reg]0x14018014=0x00000101
[740] [DISP][mipitx/reg]0x14018050=0x00000001
[740] [DISP][mipitx/reg]0x14018060=0x00000000
[740] [DISP][mipitx/reg]0x14018060=0x00000001
[740] [DISP][mipitx/reg]0x14018040=0x00000082
[740] DISP/[DISP] - kernel - DSI_PHY_TIMCONFIG, Cycle Time = 17(ns), Unit Interval = 3(ns). , lane# = 4
[740] DISP/[DISP] - kernel - DSI_PHY_TIMCONFIG, HS_TRAIL = 120, HS_ZERO = 9, HS_PRPR = 4, LPX = 4, TA_GET = 20, TA_SURE = 6, TA_GO = 16, CLK_TRAIL = 6, CLK_ZERO = 23, CLK_HS_PRPR = 3
[740] DSI_PHY_TIMCONFIG, 0x78090404,0x08140610,0x06170100,0x00080e03
[1100] [DISP]func|DSI_set_cmdq
[1100] [DISPCHECK]DSI_set_cmdq, module=dsi0 , cmdq=0x00000000
[1100] [DISP] - kernel - DSI_set_cmdq. DSI_CMDQ+0000 : 0x00063902
[1100] [DISP] - kernel - DSI_set_cmdq. DSI_CMDQ+0004 : 0x8198ffff
[1100] [DISP] - kernel - DSI_set_cmdq. DSI_CMDQ+0008 : 0x00000104
[1120] [DISP]func|DSI_set_cmdq
[1120] [DISPCHECK]DSI_set_cmdq, module=dsi0 , cmdq=0x00000000
[1140] [DISP] - kernel - DSI_set_cmdq. DSI_CMDQ+0000 : 0x00033700
[1140] [DISP]func|DSI_dcs_read_lcm_reg_v2
[1140] DISP/ Start polling DSI read ready!!!
[1180] DISP/ Polling DSI read ready timeout!!!
[1180] DSI0 state:Waiting RX-read data
[1180] DSI Mode: lane num: transfer count: status: [1180] ---------- Start dump DSI0 registers ----------
[1180] DSI+0000 : 0x00000001  0x00000000  0x00000000  0x80000000
[1180] DSI+0010 : 0x00000000  0x00000000  0x0000007c  0x00030870
[1180] DSI+0020 : 0x00000008  0x00000010  0x00000010  0x00000500
[1180] DSI+0030 : 0x00000000  0x00000000  0x00000000  0x00000000
[1180] DSI+0040 : 0x00000000  0x00000000  0x00000000  0x00000000
[1180] DSI+0050 : 0x0000001c  0x00000104  0x000000e4  0x00000000
[1180] DSI+0060 : 0x00000001  0x00010000  0x00000000  0x00000000
[1180] DSI+0070 : 0x00000000  0x00000000  0x00000000  0x00000000
[1180] DSI+0080 : 0x00000000  0x00000000  0x00000020  0x00000000
[1190] DSI+0090 : 0x0000003c  0x00000000  0x00000000  0x00000000
[1200] DSI+00a0 : 0x00060080  0x00002000  0x00000000  0x00000000
[1200] DSI+00b0 : 0x00000000  0x00000000  0x00000000  0x00000000
[1200] DSI+00c0 : 0x00000000  0x00000000  0x00000000  0x00000000
[1200] DSI+00d0 : 0x00000000  0x00000000  0x00000000  0x00000000
[1200] DSI+00e0 : 0x00000000  0x00000000  0x00000000  0x00000000
[1200] DSI+00f0 : 0x00000000  0x00000000  0x00000000  0x00000000
[1200] DSI+0100 : 0x00000055  0x00000000  0x00000000  0x000000b8
[1200] DSI+0110 : 0x78090404  0x08140610  0x06170100  0x00080e03
[1200] DSI+0120 : 0x00000000  0x00000000  0x00000000  0x00000000
[1200] DSI+0130 : 0x00000021  0x00000000  0x00000000  0x00000000
[1200] DSI+0140 : 0x00000000  0x00000000  0x00010001  0x01010100
[1200] DSI+0150 : 0x01080001  0x01010101  0x00000101  0x10000000
[1200] DSI+0160 : 0x00010200  0x00000001  0x00000000  0x00000000
[1210] DSI+0170 : 0x00000000  0xfff00000  0x00000000  0x00200000
[1220] DSI_CMD+0000 : 0x00000604  0x8198ffff  0x00000104  0x65c96dc6
[1220] DSI_CMD+0010 : 0x1fb52006  0x60160a3e  0xd9e50d77  0x5c42a90f
[1220] DSI_CMD+0020 : 0x787b9491  0x28f55582  0x10657df7  0xe3f39022
[1220] DSI_CMD+0030 : 0x2838feb6  0x9cb8d0d0  0x69527205  0xf6b5d582
[1220] DSI_CMD+0040 : 0xa2ee65c0  0xd474745e  0x11cfefd0  0xd1d41e17
[1220] DSI_CMD+0050 : 0x705d471d  0x57491712  0x5fc7505e  0xd27597c7
[1220] DSI_CMD+0060 : 0x5af0125b  0x5f53104f  0xd51b97fb  0x8e2651ad
[1220] DSI_CMD+0070 : 0xd736f643  0x8124585e  0x1f52c105  0xdd949d95
[1220] DSI_CMD+0080 : 0x4712c353  0xc6800d11  0x84554fb7  0xebd45444
[1220] DSI_CMD+0090 : 0x4b067445  0x84751146  0x733f15bd  0x19936d6f
[1220] DSI_CMD+00a0 : 0xb3530de1  0x0d17e508  0x4a246d30  0x6551df1c
[1220] DSI_CMD+00b0 : 0x42686bd1  0xf9287cf8  0xd37f0991  0xdacd707a
[1220] DSI_CMD+00c0 : 0x9cdb8955  0x1f82e1ce  0x20f0f876  0xbb17fd0e
[1240] DSI_CMD+00d0 : 0x533b98ba  0x04535bdc  0xe79a65ff  0x3421dbb1
[1240] DSI_CMD+00e0 : 0xefb40d55  0x1cdde64f  0x3f575591  0x521bd001
[1240] DSI_CMD+00f0 : 0x232d15d5  0x45572548  0xa4c47f4d  0x14749f66
[1240] DSI_CMD+0100 : 0x735f78cf  0x44fb44e5  0x57ec5513  0xf96a4dd8
[1240] DSI_CMD+0110 : 0xb8411748  0x79754808  0xae674c55  0x77d36f37
[1240] DSI_CMD+0120 : 0x91711452  0x559d6c32  0x96cc3dad  0x039aa1d2
[1240] DSI_CMD+0130 : 0x557d7205  0x8edd7656  0x278375e5  0xcd5fd157
[1240] DSI_CMD+0140 : 0x575cd67d  0xdc3c4919  0xe1d93340  0x9169999b
[1240] DSI_CMD+0150 : 0x419ed5d8  0xf26fcd50  0x73f50cc1  0xa8096178
[1240] DSI_CMD+0160 : 0xa6735b55  0x42d93d56  0x71d674db  0xbcd18bfd
[1240] DSI_CMD+0170 : 0xc7f817c8  0x5d75c925  0xf6b59901  0xd33735b9
[1240] DSI_CMD+0180 : 0xb55dd961  0x371417e8  0xd9596103  0x9e6bf1f1
[1240] DSI_CMD+0190 : 0x14d91fd5  0x08c30938  0x55478378  0x4eb22503
[1260] DSI_CMD+01a0 : 0xdd572651  0x179d3d1f  0xfbd09750  0xdfbf9407
[1260] DSI_CMD+01b0 : 0x92d1e931  0x9ad8cf8b  0x94e0e442  0x9a79b5d5
[1260] DSI_CMD+01c0 : 0x4
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