hdlbits练习题答案（更新中）

最新推荐文章于 2025-07-25 08:31:21 发布

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本文分享了作者在学习Verilog过程中在HDLBits网站上的练习题答案，涵盖基础知识、向量和模块层次等内容，旨在促进学习交流。

最近在学习Verilog，发现hdlbits是个挺不错的练习网站。以下是我自己做的答案，希望与大家一起交流、进步。（本博客将持续更新）

Verilog Language

Basics

Wire

module top_module( input in, output out );
    assign out = in;
endmodule

Wire4

module top_module( input a,b,c, output w,x,y,z );
    assign w = a;
    assign x = b;
    assign y = b;
    assign z = c;
endmodule

notgate

module top_module( input in, output out );
    assign out = ~in;
endmodule

andgate

module top_module( input a, input b, output out );
    assign out = a&b;
endmodule

norgate

module top_module( input a, input b, output out );
    assign out = ~(a|b);
endmodule

xorgate

module top_module( input a, input b, output out );
    assign out = (a&b)|(~a&~b);
endmodule

wire decl

module top_module( input a, input b, input c, input d, output out, output out_n   ); 
    wire ab_and,cd_and;
    assign ab_and = a&b;
    assign cd_and = c&d;
    assign out = ab_and | cd_and;
    assign out_n = ~out;
endmodule

7458

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
    
    assign p1y = (p1a&p1b&p1c)|(p1d&p1e&p1f);
    assign p2y = (p2a&p2b)|(p2c&p2d);

endmodule

Vectors

Vector0

module top_module ( 
    input wire [2:0] vec,
    output wire [2:0] outv,
    output wire o2,
    output wire o1,
    output wire o0  ); // Module body starts after module declaration
    
    assign outv = vec;
    assign o2 = vec [2];
    assign o1 = vec [1];
    assign o0 = vec [0];

endmodule

vector1

module top_module( 
    input wire [15:0] in,
    output wire [7:0] out_hi,
    output wire [7:0] out_lo );
    
    assign out_hi = in[15:8];
    assign out_lo = in[7:0];

endmodule

vector2

module top_module( 
    input [31:0] in,
    output [31:0] out );//

    assign out[31:24] = in[7:0];
    assign out[23:16] = in[15:8];
    assign out[15:8] = in[23:16];
    assign out[7:0] = in[31:24];

endmodule

vectorgates

module top_module( 
    input [2:0] a,
    input [2:0] b,
    output [2:0] out_or_bitwise,
    output out_or_logical,
    output [5:0] out_not
);
    
    assign out_or_bitwise = a|b;
    assign out_or_logical = a||b;
    assign out_not[2:0] = ~a;
    assign out_not[5:3] = ~b;

endmodule

gates4

module top_module( 
    input [3:0] in,
    output out_and,
    output out_or,
    output out_xor
);
    
    assign out_and = in[0]&in[1]&in[2]&in[3];
    assign out_or = in[0]|in[1]|in[2]|in[3];
    assign out_xor = in[0]^in[1]^in[2]^in[3];

endmodule

vector3

module top_module (
    input [4:0] a, b, c, d, e, f,
    output [7:0] w, x, y, z );//

    assign {w,x,y,z} = {a,b,c,d,e,f,2'b11};

endmodule

vectorr

module top_module( 
    input [7:0] in,
    output [7:0] out
);
    assign out = {in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7]};

endmodule

vector4

module top_module (
    input [7:0] in,
    output [31:0] out );//

    assign out = {{24{in[7]}},in};

endmodule

vector5

module top_module (
    input a, b, c, d, e,
    output [24:0] out );//

    assign out = ~{{5{a}},{5{b}},{5{c}},{5{d}},{5{e}}}^{5{a,b,c,d,e}};
endmodule

Modules: Hierarchy

Module

module top_module ( input a, input b, output out );
    
    mod_a instance1 (.out(out), .in1(a), .in2(b));

endmodule

Module pos

module top_module ( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);
    
    mod_a inst1 (out1,out2,a,b,c,d);

endmodule

Module name

module top_module ( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);
    
    mod_a inst1 (.in1(a), .in2(b), .in3(c), .in4(d), .out1(out1), .out2(out2));

endmodule

Module shift

module top_module ( input clk, input d, output q );
    
    wire o1,o2;
    my_dff ff1 (.clk(clk),.d(d),.q(o1));
    my_dff ff2 (.clk(clk),.d(o1),.q(o2));
    my_dff ff3 (.clk(clk),.d(o2),.q(q));

endmodule

Module shitf8

module top_module ( 
    input clk, 
    input [7:0] d, 
    input [1:0] sel, 
    output [7:0] q 
);
    wire [7:0] q1,q2,q3,s0,s1;
    my_dff8 ff1 (clk,d,q1);
    my_dff8 ff2 (clk,q1,q2);
    my_dff8 ff3 (clk,q2,q3);
    assign s0 = {8{sel[0]}};
    assign s1 = {8{sel[1]}};
    assign q = (~s0&~s1&d)|(~s1&s0&q1)|(s1&~s0&q2)|(s1&s0&q3);

endmodule

Module add

module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    wire w1;
    add16 add1 (a[15:0],b[15:0],0,sum[15:0],w1);
    add16 add2 (a[31:16],b[31:16],w1,sum[31:16]);
endmodule

Module fadd

module top_module (
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);//
    wire w1;
    add16 a1 (a[15:0],b[15:0],0,sum[15:0],w1);
    add16 a2 (a[31:16],b[31:16],w1,sum[31:16]);

endmodule

module add1 ( input a, input b, input cin,   output sum, output cout );

// Full adder module here
    assign sum = a^b^cin;
    assign cout = a&b|a&cin|b&cin;

endmodule

Module cseladd

module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    wire [15:0] s0,s1,co1;
    add16 adder1 (a[15:0],b[15:0],0,sum[15:0],co1[0]);
    add16 adder2 (a[31:16],b[31:16],0,s0);
    add16 adder3 (a[31:16],b[31:16],1,s1);
    assign co1 = {16{co1[0]}};
    assign sum[31:16] = co1&s1|s0&~co1;

endmodule

Module addsub

module top_module(
    input [31:0] a,
    input [31:0] b,
    input sub,
    output [31:0] sum
);
    
    wire [31:0] xoro;
    wire w1;
    assign xoro = b^{32{sub}};
    add16 adder1 (a[15:0],xoro[15:0],sub,sum[15:0],w1);
    add16 adder2 (a[31:16],xoro[31:16],w1,sum[31:16]);

endmodule

标签

#verilog