LLVM Plumbs Support For Intel Golden Cove's New SERIALIZE Instruction

Yesterday we noted Intel's programming reference manual being updated with new Golden Cove instructions for Sapphire Rapids and Alder Lake and with that Intel's open-source developers have begun pushing their changes to the compilers. The latest updates add TSXLDTRK, a new HYBRID bit for Core+Atom hybrid CPUs, and a new SERIALIZE instruction. After GCC was receiving the patch attention yesterday, LLVM is getting its attention today.

Being merged today to LLVM 11 is support for Intel's new SERIALIZE instruction for those 2021 processors.

As outlined yesterday, the SERIALIZE instruction for Alder Lake and Sapphire Rapids will serialize the instruction execution. SERIALIZE will make sure that all modifications to flags / registers / memory by previous instructions are complete and all buffered writes are pushed to memory.

LLVM now has support for SERIALIZE and for now is just enabled with the -mserialize flag but not enabled for any CPU target yet. The performance impact of SERIALIZE is likely to be quite significant while we await to see Intel's future guidance about their recommended usage of SERIALIZE over existing serializing instructions.

Also ready to land for LLVM is TSXLDTRK instructions as another one of the newly-published additions for Golden Cove. TSXLDTRK is Intel TSX Suspend Load Address Tracking.

LLVM/Clang 11.0 should be out in September~October and will likely have good Sapphire Rapids / Alder Lake CPU support in place well ahead of their anticipated launches in 2021.