Fix vector load/store instruction large displacement bug - #3531
Conversation
|
We really ought to add Tril testing for such cases. This would have been caught long ago. @Leonardo2718 do we have a timeline when we may support processor detection for Tril testing? Such a test for this bug would have required z13 machines. |
NigelYiboYu
changed the title
|
I'm currently working on a more complete fix. Marking this WIP. |
#3539 🙂 |
8784f91 to
f8042f4
Compare
| return new (INSN_HEAP) TR::S390VRSaInstruction(cg, op, n, targetReg, sourceReg, mr, mask4); | ||
| if (mr != NULL) preced = mr->enforceSSFormatLimits(n, cg, preced); | ||
|
|
||
| if (preced) |
There was a problem hiding this comment.
A comment on the use of two different constructors here because I can't find a better place to put it. We have to use two constructors here for a lot of instruction formats because the root OMR::Instruction has two constructors and they use different preceding instructions. We can misplace an instruction if the preceding instruction is not used properly.
f8042f4 to
295f553
Compare
NigelYiboYu
changed the title
295f553 to
ff73b67
Compare
Fix a problem in VRS, VSI, and VRV vector-storage instruction formats to handle large displacements correctly. The fix consists of two parts: an instruction selection phase change and a binary encoding change. Both of these changes aim to use a scratch register to hold the base+displacement value if a vector load/store instruction has a displacement that exceeds the 12-bit signed integer range. Signed-off-by: Nigel Yu <yunigel@ca.ibm.com>
|
@genie-omr build all |
|
AppVeoyr failed due to infrastructure reasons. |
3 participants
Fix vector load/store instruction large displacement bug
Fix a problem in VRS, VSI, and VRV vector-storage instruction
formats to handle large displacements correctly.
The fix consists of two parts: an instruction selection phase change and
a binary encoding change. Both of these changes aim to use a scratch register
to hold the base+displacement value if a vector load/store instruction has a
displacement that exceeds the 12-bit signed integer range.
Signed-off-by: Nigel Yu yunigel@ca.ibm.com