牛客网verilog VL17 用3-8译码器实现全减器

最新推荐文章于 2024-09-19 20:18:02 发布

原创最新推荐文章于 2024-09-19 20:18:02 发布 · 256 阅读

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GEO检测

文章详细描述了使用Verilog语言编写的模块decoder_38，它是一个3-8译码器，根据输入信号控制输出线。另一个模块decoder1则将3-8译码器的结果应用于全减器功能，包括计算差值和高位借位。

`timescale 1ns/1ns

module decoder_38(
   input             E      ,
   input             A0     ,
   input             A1     ,
   input             A2     ,
   
   output reg       Y0n    ,  
   output reg       Y1n    , 
   output reg       Y2n    , 
   output reg       Y3n    , 
   output reg       Y4n    , 
   output reg       Y5n    , 
   output reg       Y6n    , 
   output reg       Y7n    
);

always @(*)begin
   if(!E)begin
      Y0n = 1'b1;
      Y1n = 1'b1;
      Y2n = 1'b1;
      Y3n = 1'b1;
      Y4n = 1'b1;
      Y5n = 1'b1;
      Y6n = 1'b1;
      Y7n = 1'b1;
   end  
   else begin
      case({A2,A1,A0})//输出0有效
         3'b000 : begin
                     Y0n = 1'b0; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; 
                     Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;
                  end 
         3'b001 : begin
                     Y0n = 1'b1; Y1n = 1'b0; Y2n = 1'b1; Y3n = 1'b1; 
                     Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;
                  end 
         3'b010 : begin
                     Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b0; Y3n = 1'b1; 
                     Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;
                  end 
         3'b011 : begin
                     Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b0; 
                     Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;
                  end 
         3'b100 : begin
                     Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; 
                     Y4n = 1'b0; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;
                  end 
         3'b101 : begin
                     Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; 
                     Y4n = 1'b1; Y5n = 1'b0; Y6n = 1'b1; Y7n = 1'b1;
                  end 
         3'b110 : begin
                     Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; 
                     Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b0; Y7n = 1'b1;
                  end 
         3'b111 : begin
                     Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; 
                     Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b0;
                  end 
         default: begin
                     Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; 
                     Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;
                  end
      endcase  
   end 
end    
     
endmodule

module decoder1(
   input             A     ,//被减数
   input             B     ,//减数
   input             Ci    ,//低位借位
   
   output wire       D     ,//差
   output wire       Co      //高位借位  
);

wire y0;
wire y1;
wire y2;
wire y3;
wire y4;
wire y5;
wire y6;
wire y7;

decoder_38 decoder1(
   .       E   (1'b1)   ,
   .       A0  (Ci)   ,
   .       A1  (B)   ,
   .       A2  (A)   ,

   .      Y0n  (y0)  ,  
   .      Y1n  (y1)  , 
   .      Y2n  (y2)  , 
   .      Y3n  (y3)  , 
   .      Y4n  (y4)  , 
   .      Y5n  (y5)  , 
   .      Y6n  (y6)  , 
   .      Y7n  (y7)  
);

assign D=!(y1&y2&y4&y7);
assign Co=!(y1&y2&y3&y7);
endmodule
//3——8译码器可实现三个变量的函数
//先写出全减器的增值表，001输入 Y1输出为0 ...    Ci是低位 对应A0
//Y1'+Y2'+Y4'+Y7'=D    D=(Y1*Y2*...)'

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