UCIE Specification详解（一）-CSDN博客

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文章目录

- Terminology（术语）

Terminology（术语）

Table 1. Terms and Definitions (Sheet 1 of 8)

Term	Definition
Ack	Acknowledge
ACPI	Advanced Configuration and Power Interface 高级配置与电源接口
Addr	Address
Advanced Package	This packaging technology is used for performance optimized applications and short reach interconnects. 这种封装技术用于性能优化的应用和短距离互连
AFE	Analog Front End 模拟前端
ALMP	ARB/MUX Link Management Packet (as defined in CXL Specification) ARB/MUX 链路管理数据包（如CXL 规范中所定义）
APMW	Advanced Package Module Width 先进封装模块宽度
ARB/MUX	Arbiter/Multiplexer (as defined in CXL Specification) 仲裁器/多路复用器（如CXL 规范中所定义）
Asset	Any data or mechanism used to access data that should be protected from illicit access, use, availability, disclosure, alteration, destruction, or theft. 任何用于访问数据的数据或机制，这些数据应受到保护，以免遭非法访问、使用、获取、披露、更改、破坏或窃取
ATE	Automated Test Equipment 自动化测试设备
B2B	Back-to-Back
BAR	Base Address Register 基址寄存器
BDF	Bus Device Function 总线设备功能
BE	Byte Enable 字节启用
BEI	BAR Equivalent Indicator BAR 等效指标
BER	Bit Error Ratio 比特误码率
BFM	Bus Functional Model 总线功能模型

Term	Definition
bubble	Gap in data transfer and/or signal transitions. Measured in number of clock cycles. 数据传输和/或信号转换中的间隔。以时钟周期数衡量
bundle	Tx group or Rx group for UCIe-3D interconnects that contains data, clock, power, and ground. A 3D Module consists of a Tx bundle and an Rx bundle. 用于UCIe-3D 互连的Tx 组或Rx 组，包含数据、时钟、电源和接地。一个3D 模块由一个Tx 束和一个Rx 束组成
C4 bump	Controller Collapse Chip Connect bump控制器折叠芯片连接凸点
CA	Completer Abort 完成方终止
CDM	Charged Device Model 带电设备模型
chiplet	Integrated circuit die that contains a well-defined subset of functionality that is designed to be combined with other chiplets in a package. 集成电路Die，其包含功能明确的子集，旨在与封装中的其他芯粒相结合
clear cleared	If clear or reset is used and no value is provided for a bit, it is interpreted as 0b. 如果使用清除或复位，且某位未提供值，则将其解释为0b
CLM	Current Lane Map 当前通道映射
CMLS	Common Maximum Link Speed 通用最大链路速度
CoWoS	Chip on Wafer on Substrate 基板上晶圆上的芯片
CPU	Central Processing Unit 中央处理器
CRC	Cyclic Redundancy Check 循环冗余校验
CXL	Compute eXpress Link
CXL 68B Flit Mode	This term is used to reference 68B Flit Mode related Protocol features defined in CXL Specification. 此术语用于引用CXL 规范中定义的68B Flit 模式相关协议特性
CXL 256B Flit	This term is used to reference 256B Flit Mode related Protocol features

Term	Definition
Mode	defined in CXL Specification. 此术语用于引用CXL 规范中定义的256B Flit 模式相关协议特性
D2C	Data-to-Clock
D2D	Die-to-Die Die-to-Die
DCC	Duty Cycle Correction

Table 1. Terms and Definitions (Sheet 2 of 8)

Term	Definition
DDR	Double Data Rate Memory 双倍数据速率内存
DevID	Device ID
DFx	Design for Debug or Design for Test 调试设计或测试设计
DLLP	Data Link Layer Packet (as defined in PCIe Base Specification) 数据链路层数据包（如PCIe 基础规范中所定义）
DLP	In Flit modes, the Data Link Layer Payload within a flit (as defined in PCIe Base Specification). 在Flit 模式中，Flit 内的数据链路层有效载荷（如PCIe 基础规范中所定义）
DMH	DFx Management Hub. DFx entity that provides enumeration/global control/status of DFx capabilities in a chiplet. DFx 管理中心。DFx 实体，在芯粒中提供DFx 能力的枚举/全局控制/状态
DMS	DFx Management Spoke. DFx entity that implements a specific test/debug functionality within a DMH. DFx 管理辐条。DFx 实体，在DFx 管理中心内实现特定的测试/调试功能
DMS-ID	Static design time ID assigned to a DMS for ID-routed messages within a DMH. Interchangeably used with the term Spoke-ID. 为DMH 内用于ID 路由消息的DMS 分配的静态设计时ID。与术语“Spoke-ID”可互换使用
Domain Reset (domain reset) 域复位	Used to refer to a hardware mechanism that sets or returns all UCIe registers and state machines associated with a given UCIe Link to their initialization values as specified in this document. It is required for both sides of the Link to have an overlapping time window such that they are both in domain reset concurrently. 用于指一种硬件机制，将与给定UCIe 链路相关的所有UCIe 寄存器和状态机设置或返回到本文档中指定的其初始化值。链路的两侧都需要有一个重叠的时间窗口，以便它们同时处于域复位状态

Term	Definition
DP	Downstream Port
DSP	Downstream Switch Port (as defined in CXL Specification)下游交换机端口（如CXL 规范中所定义）
DVFS	Dynamic Voltage Frequency Scaling 动态电压频率调整
DVSEC	Designated Vendor-Specific Extended Capability (as defined in PCIe Base Specification) 指定的供应商特定扩展能力（如PCIe 基础规范中所定义）
DWORD	Double Word. Four bytes. When used as an addressable quantity, a Double Word is four bytes of data that are aligned on a four-byte boundary (i.e., the least significant two bits of the address are 00b). 双字。四个字节。当用作可寻址量时，双字是四个字节的数据，在四字节边界上对齐（即，地址的最低有效两位是00b）
E2E	End to end 端到端
EM	Eye Margin 眼图余量
EMIB	Embedded Multi-die Interconnect Bridge嵌入式多die 互连桥
EML	Eye Margin Left 左眼图余量
EMR	Eye Margin Right 右眼图余量
EMV	Eye Margin Valid 眼图余量有效
Encapsulated MTP eMTP	Encapsulated Management Transport Packet. The resulting packet after Encapsulation. 封装管理传输数据包。封装后的结果数据包
Encapsulation	Process of splitting an MTP or Vendor defined messages (exchanged between Management Port Gateways on both ends of a link) into smaller pieces to meet any required payload length restrictions or for any other reasons like credit availability, adding a 2-DWORD header to each piece and if required, adding a 1-DWORD data padding at the end of an MTP to transmit the MTP over sideband or mainband UCIe link. In the case of an MTP, the resulting packet after Encapsulation is called the Encapsulated MTP. 将MTP 或供应商定义的消息（在链路两端的管理端口网关之间交换）分割成较小部分的过程，以满足任何所需的有效载荷长度限制或出于其他原因（如信用可用性），为每个部分添加一个2 双字的头，如果需要，在MTP 的末尾添加一个1-DWORD 的数据填充，以便通过边带或主带UCIe 链路传输MTP。对于MTP，封装后的结果数据包称为Encapsulated MTP

Term	Definition
Endpoint EP	As defined in PCIe Base Specification.如PCIe 基础规范中所定义
eRCD	Exclusive Restricted CXL Device (as defined in CXL Specification)排他性受限CXL 设备（如CXL 规范中所定义）
eRCH	Exclusive Restricted CXL Host (as defined in CXL Specification)排他性受限CXL 主机（如CXL 规范中所定义）
ESD	Electro-Static Discharge 静电放电
F2B	Face-to-Back
F2F	Face-to-Face
FDI	Flit-Aware Die-to-Die Interface Flit 感知Die-to-Die 接口
FEC	Forward Error Correction 前向纠错
FEXT	Far-End CrossTalk 远端串扰
FH	Flit Header

Table 1. Terms and Definitions (Sheet 3 of 8)

Term	Definition
FIFO	First In, First Out 先进先出
FIR	Finite Impulse Response 有限脉冲响应
FIT	Failure In Time. 1 FIT = 1 device failure in 109hours. 故障时间。1 FIT = 每109小时1 次设备故障

Term	Definition
Flit	Link Layer unit of transfer (as defined in CXL Specification). 链路层传输单元（如CXL 规范中所定义）
Flit Marker FM	Flit Marker (as defined in PCIe Base Specification) Flit Marker （如PCIe 基础规范中所定义）
FW	Firmware
FW-CLK	Forwarded Clock over the UCIe Link for mainband data Lanes 通过UCIe 链路为基带数据通道转发的时钟
HMLS	Highest Maximum Link Speed of next-lower configuration. 次低配置的最高最大链路速度
Hub	See DMH.
HW	Hardware
IL	Insertion Loss 插入损耗
I/O	Input/Output
IP	Generic term used to refer to architecture blocks that are defined within the specification (e.g., D2D adapter, PHY, etc.). 用于指代规范中定义的架构块的通用术语（例如，D2D 适配器、PHY等）
IPA	Ignore Prohibited Access 忽略禁止访问
ISI	Inter-Symbol Interference 符号间干扰
KPI	Key Performance Indicator 关键绩效指标
Lane	A pair of signals mapped to physical bumps, one for Transmission, and one for Reception. A xN UCIe Link is composed of N Lanes. 一对映射到物理凸点的信号，一个用于发送，一个用于接收。一个xN的UCIe 链路由N 个通道组成
LCLK	Refers to the clock at which the Logical Physical Layer, Adapter and RDI/FDI are operating. 指逻辑物理层、适配器和RDI/FDI 运行的时钟
LCRC	Link CRC
LFSR	Linear Feedback Shift Register 线性反馈移位寄存器
Link UCIe Link	A Link or UCIe Link refers to the set of two UCIe components and their interconnecting Lanes which forms a dual-simplex communications path between the two components. 链路或UCIe 链路指的是两个UCIe 组件及其互连通道的集合，这些通道在两个组件之间形成了双工通信路径

Term	Definition
LSM	Adapter Link State Machine 适配器链路状态机
LTSM	Link Training State Machine 链路训练状态机
LTSSM	Link Training and Status State Machine (as defined in PCIe Base Specification) 链路训练和state 状态机（如PCIe 基础规范中所定义）
LSB	Least Significant Bit
Mainband MB	Connection that constitutes the main data path of UCIe. Consists of a forwarded clock, a data valid pin, and N Lanes of data per module. 构成UCIe 主要数据路径的连接。由转发时钟、数据有效引脚和每个模块的N 个数据通道组成
Management Bridge	Type of Management Entity that bridges a Management Network within an SiP to another network that may be internal or external to the SiP. 一种管理实体类型，将SiP 内的管理网络桥接到可能在SiP 内部或外部的另一个网络
Management Director	Management Element that is responsible for discovering, configuring, and coordinating the overall management of the SiP and acts as the manageability Root of Trust (RoT). 负责发现、配置和协调SiP 整体管理，并作为可管理性信任根（RoT）的管理元素
Management Domain	One or more chiplets in an SiP that are interconnected by a Management Network and support UCIe Manageability. SiP 中的一个或多个芯粒，它们通过管理网络互连并支持UCIe 可管理性
Management Element	Type of Management Entity that can perform one or more management functions. 能够执行一个或多个管理功能的管理实体类型
Management Entity	Addressable entity on the Management Network that can send and/or receive UCIe Management Transport packets. A Management Element, a Management Port, and a Management Bridge are all a type of Management Entity. 管理网络上可寻址的实体，能够发送和/或接收UCIe 管理传输数据包。管理元素、管理端口和管理桥都是管理实体的一种类型

Term	Definition
Management Flit	A Flit that carries a Management Port Message (MPM).携带管理端口消息（MPM）的Flit
Management Link Encapsulation Mechanism 管理链路封装机制	Mechanism that defines how UCIe Management Transport packets are transferred across a point-to- point management link. 定义UCIe 管理传输数据包如何在点到点管理链路上传输的机制

Table 1. Terms and Definitions (Sheet 4 of 8)

Term	Definition
Management Network	Network within and between chiplets that is capable of transporting UCIe Management Transport packets. 芯粒内部和之间能够传输UCIe 管理传输数据包的网络
Management Port	Management Entity that facilitates management communication between chiplets using a chiplet- to-chiplet management link. 使用芯粒到芯粒管理链路促进芯粒之间管理通信的管理实体
Management Port Gateway 管理端口网关 (MPG)	Entity that provides the bridging functionality when transporting an MTP from/to a local SoC management fabric (which is an SoC-specific implementation) to/from a UCIe link. 在将MTP 从本地SoCManagement Fabric（这是特定于SoC 的实现）传输到UCIe 链路传输或从UCIe 链路传输到本地SoCManagement Fabric时，提供桥接功能的实体
Management Port Message 管理端口消息（MPM）	Sideband or mainband message that relates to encapsulation. 与封装相关的边带或主带消息
Management Protocol	Protocol carried on top of the UCIe Management Transport. 在UCIe 管理传输之上承载的协议
Management Reset	Type of reset that causes all UCIe manageability and manageability structures in a chiplet to be reset to their default state. 一种复位类型，导致芯粒中的所有UCIe 可管理性和可管理性结构被复位到其默认状态
MCLS	Number of active 活动的Modules Current Link Speed 数量
MMIO	Memory mapped Input/Output 内存映射输入/输出

Term	Definition
MMPL	Multi-module PHY Logic 多模块PHY 逻辑
Module	UCIe main data path on the physical bumps is organized as a group of Lanes called a Module. For Standard Package, 16 Lanes constitute a single Module. For Advanced Package, 64 Lanes constitute a single Module.物理凸点上的UCIe 主数据路径被组织为一组称为模块的通道。对于标准封装，16 个通道构成一个模块。对于先进封装，64 个通道构成一个模块
MSB	Most Significant Bit 最高有效位
MTP	Management Transport Packet 管理传输数据包
Nak	Negatively acknowledge 否定确认
NEXT	Near-End CrossTalk 近端串扰
NOP	No Operation 无操作
NVMe	Non-Volatile Memory express 非易失性内存主机控制器接口规范
One-Time Programmable	Any data storage mechanism that is capable of being programmed only once (e.g., fuse). 任何只能被编程一次的数据存储机制（例如，熔丝）
P2P	Peer to peer 对等
Packet	A block of data transmitted across a network.通过网络传输的数据块
PCIe (PCI Express)	Peripheral Component Interconnect Express (defined in PCIe Base Specification) 外围组件互连高速（在PCIe 基础规范中定义）
PCIe Flit Mode	This term is used to reference Flit Mode related Protocol features defined in PCIe Base Specification. 该术语用于引用PCIe 基础规范中定义的与Flit 模式相关的协议特性
PCIe non-Flit Mode	This term is used to reference non-Flit Mode related Protocol features defined in PCIe Base Specification. 该术语用于引用PCIe 基础规范中定义的非Flit 模式相关的协议特性

Term	Definition
PDOS	Permanent Denial of Service 永久性拒绝服务
PDS	Pause of Data Stream 数据流暂停
PHY	Physical Layer (PHY and Physical Layer are used interchangeable throughout the Specification) 物理层（在整个规范中，PHY 和物理层可互换使用）
PI	Phase Interpolator 相位内插器
PLL	Phase-Locked Loop 锁相环
PM	Power Management states, used to refer to behavior and/or rules related to Power Management states (covers both L1 and L2). 电源管理状态，用于指与电源管理状态相关的行为和/或规则（涵盖L1和L2）
PMO	Sideband Performance Mode Operation边带高性能模式操作
QWORD	Quad Word. Eight bytes. When used as an addressable quantity, a Quad Word is eight bytes of data that are aligned on an eight-byte boundary (i.e., the least significant three bits of the address are 000b). 四字。八个字节。当用作可寻址量时，四字是在八字节边界上对齐的八个字节的数据（即，地址的最低有效三位是000b）
RAC	Read Access Control 读取访问控制
RCD	Restricted CXL Device (as defined in CXL Specification)受限CXL 设备（如CXL 规范所定义）
RCH	Restricted CXL Host (as defined in CXL Specification)受限CXL 主机（如CXL 规范所定义）
RCiEP	Root Complex Integrated Endpoint 根复合体集成端点

Table 1. Terms and Definitions (Sheet 5 of 8)

Term	Definition
RCKN_P RXCKN rxckn	Physical Lane for Clock Receiver Phase-2 Clock 接收器相位2 的物理通道

Term	Definition
RCKP_P RXCKP rxckp	Physical Lane for Clock Receiver Phase-1 Clock 接收器相位1 的物理通道
RCRB	Root Complex Register Block 根复合体寄存器块
RDI	Raw Die-to-Die Interface 原始Die-to-Die 接口
RD_P[N] RD PN RXDATA[N] rxdataN	Nth Physical Lane for Data Receiver Data 接收器的第N 个物理通道
remote Link partner	This term is used throughout this specification to denote the logic associated with the far side of the UCIe Link; to denote actions or messages sent or received by the Link partner of a UCIe Die. 在本规范中，该术语用于表示与UCIe 链路远端相关的逻辑；表示UCIe Die 的链路伙伴发送或接收的动作或消息
Replay Retry	Retry and Replay are used interchangeably to refer to the Link level reliability mechanisms. 重试和重放可互换使用，以指代链路级可靠性机制
Reserved	The contents, states, or information are not defined at this time. Using any Reserved area (for example, packet header bit-fields, configuration register bits) is not permitted. Reserved register fields must be read only and must return 0 (all 0s for multi-bit fields) when read. For packets transmitted and received over the UCIe Link (mainband or sideband), the Reserved bits must be cleared to 0b by the sender and ignored by the receiver. Reserved encodings for register and packet fields must not be used. Any implementation dependence on a Reserved field value or encoding will result in an implementation that is not UCIe-compliant. The functionality of such an implementation cannot be guaranteed in this or any future revision of this specification. For registers, UCIe uses the “RsvdP” or “RsvdZ” attributes for reserved fields, as well as Rsvd, and these follow the same definition as PCIe Base Specification for hardware as well as software . 此时未定义内容、状态或信息。不允许使用任何保留区域（例如，数据包报头位字段、配置寄存器位）。保留的寄存器字段必须为只读，并且读取时必须返回0（对于多位字段，全部为0）。对于通过UCIe 链路（主带或边带）发送和接收的数据包，发送方必须将保留位清除为0b，接收方必须忽略。不得使用寄存器和数据包字段的保留编码。任何依赖于保留字段值或编码的实现都将导致不符合UCIe 规范的实现。在此规范的此版本或任何未来版本中，无法保证此类实现的功能。对于寄存器，UCIe 对保留字段使用“RsvdP”或“RsvdZ”属性，以及Rsvd，并且这些属性与PCIe 基础规范中对硬件和软件的定义相同

Term	Definition
reset	If reset or clear is used and no value is provided for a bit, it is interpreted as 0b. 如果使用了复位或清零，并且未为某位提供值，则将其解释为0b
RID	Revision ID
RL	Register Locator
Root Complex	As defined in PCIe Base Specification. 如PCIe 基础规范中所定义
Root Port RP	As defined in PCIe Base Specification. 如在PCIe 基础规范中所定义
RoT	Root of Trust
RRDCK P RXCKRD rxckRD	Physical Lane for redundant Clock/Track Receiver 冗余时钟/Track 接收器的物理通道
RRD_P[N] RRD PN RXDATARD[N] rxdataRD[N]	Nth Physical Lane for redundant Data Receiver 冗余Data 接收器的第N 个物理通道
RRDVLD P RXVLDRD rxvldRD	Physical Lane for redundant Valid Receiver 冗余有效接收器的物理通道
RTRK P RXTRK rxtrk	Physical Lane for Track Receiver Track 接收器的物理通道
RVLD P RXVLD rxvld	Physical Lane for Valid Receiver 有效接收器的物理通道
Rx	Receiver

Table 1. Terms and Definitions (Sheet 6 of 8)

Term	Definition
RXCKSB rxcksb	Physical Lane for sideband Clock Receiver 边带Clock 接收器的物理通道
RXCKSBRD	Physical Lane for redundant sideband Clock Receiver 冗余边带Clock 接收器的物理通道

Term	Definition
RXDATASB rxdatasb	Physical Lane for sideband Data Receiver 边带Data 接收器的物理通道
RXDATASBRD rxdatasbRD	Physical Lane for redundant sideband Data Receiver 冗余边带Data 接收器的物理通道
SBFE	Sideband Feature Extensions 边带功能扩展
{<SBMSG>}	Sideband message requests or responses are referred to by their names enclosed in curly brackets. See Chapter 7.0 for the mapping of sideband message names to relevant encodings. An asterisk in the <SBMSG> name is used to denote a group of messages with the same prefix or suffix in their name. 边带消息请求或响应由括在花括号中的名称来指代。有关边带消息名称到相关编码的映射，请参阅第7.0 章。<SBMSG> 名称中的星号用于表示名称具有相同前缀或后缀的一组消息
SC	Successful Completion
SD	Security Director. Management Element that may configure security parameters. 安全主管。可配置安全参数的管理元素
Segmentation	Process of taking a large MTP, splitting it into smaller “segments” and sending those segments on multiple sideband links or mainband stacks.将一个大的MTP 进行分割，分成较小的“段”，并在多个边带链路或主带栈上发送这些段的过程
SERDES	Serializer/Deserializer
serial packet	A 64-bit serial packet is defined on the sideband I/O interface to the remote chiplet as shown in Figure 4-8. 如图4-8 所示，在到远程芯粒的边带I/O 接口上定义了一个64 位串行数据包
set	If set is used and no value is provided for a bit, it is interpreted as 1b. 如果使用了置位，并且未为某位提供值，则将其解释为1b
SFES	Sideband Feature Extensions Supported 支持的边带功能扩展
Sideband SB	Connection used for parameter exchanges, register accesses for debug/compliance and coordination with remote partner for Link training and management. Consists of a forwarded clock pin and a data pin in each direction. The clock is fixed at 800 MHz regardless of the main data path speed. The sideband logic for the UCIe Physical Layer must be on auxiliary power and an “always on” domain. Each module has its own set of sideband pins. 用于参数交换、调试/合规性的寄存器访问以及与远程伙伴协调链路训练和管理的连接。由每个方向上的一个转发时钟引脚和一个数据引脚组成。无论主数据路径速度如何，时钟固定为800 MHz。UCIe 物理层的边带逻辑必须在辅助电源和“always on”域上。每个模块都有自己的一组边带引脚

Term	Definition
SiP	System in Package. Collection of chiplets packaged as a unit. 系统级封装。作为一个单元封装的芯粒集合
SM	State Machine 状态机
SO	Sideband-only
SoC	System on a Chip 片上系统
Spoke	See DMS.
Standard Package	This packaging technology is used for low cost and long reach interconnects using traces on organic package/substrate 这种封装技术用于在有机封装/基板上使用走线实现低成本和长距离互连
Strobe	Used interchangeably with clock for sideband clock 与边带时钟的“时钟”可互换使用
SW	Software
TC	Traffic Class 流量类别
TCKN_P TXCKN txckn	Physical Lane for Clock Transmitter Phase-2 Clock 发送器相位2 的物理通道
TCKP_P TXCKP txckp	Physical Lane for Clock Transmitter Phase-1 Clock 发送器相位1 的物理通道
TCM	Tightly coupled mode
TDPI	Test, Debug, Pattern, and Infrastructure 测试、调试、模式和基础设施

Table 1. Terms and Definitions (Sheet 7 of 8)

Term	Definition
TD_P[N] TD_PN TXDATA[N] txdataN	Nth Physical Lane for Data Transmitter 数据发送器的第N 个物理通道
TLP	Transaction Layer Packet (as defined in PCIe Base Specification) 事务层数据包（如PCIe 基础规范中所定义）
TRD_P[N] TRD_PN TXDATARD[N] txdataRD[N]	Nth Physical Lane for redundant Data Transmitter 冗余数据发送器的第N 个物理通道
TRDCK_P TXCKRD txckRD	Physical Lane for redundant Clock/Track Transmitter 冗余时钟/Track 发送器的物理通道
TRDVLD_P TXVLDRD txvldRD	Physical Lane for redundant Valid Transmitter 冗余有效发送器的物理通道
Trx	Transceiver
TSV	Through-Silicon Via
TTRK_P TXTRK txtrk	Physical Lane for Track Transmitter Track 发送器的物理通道
TVLD_P TXVLD txvld	Physical Lane for Valid Transmitter 有效发送器的物理通道
Tx	Transmitter
TXCKSB txcksb	Physical Lane for sideband Clock Transmitter 边带Clock 发送器的物理通道
TXCKSBRD txcksbRD	Physical Lane for redundant sideband Clock Transmitter 冗余边带Clock 发送器的物理通道
TXDATASB txdatasb	Physical Lane for sideband Data Transmitter 边带数据发送器的物理通道
TXDATASBRD txdatasbRD	Physical Lane for redundant sideband Data Transmitter 冗余边带数据发送器的物理通道
TXEQ	Transmitter Equalization 发送器均衡

Term	Definition
UCIe	Universal Chiplet Interconnect express 通用芯粒互连快速
UCIe-3D	Universal Chiplet Interconnect express for 3D packaging 用于3D 封装的通用芯粒互连快速
UCIe-A	Used to denote x64 Advanced Package module. 用于表示x64 Advanced Package 模块
UCIe-A x32	Used to denote x32 Advanced Package module. See Chapter 5.0 for UCIe-A x32 Advanced Package bump matrices, and interoperability between x32 to x32 and x32 to x64 module configurations. 用于表示x32 Advanced Package 模块。有关UCIe-A x32 Advanced 封装凸块矩阵以及x32 与x32 和x32 与x64 模块配置之间的互操作性，请参阅第5.0 章
UCIe-S	Used to denote x16 Standard Package module. 用于表示x16 标准封装模块
UCIe chiplet	A chiplet that complies with the UCIe specification. 符合UCIe 规范的芯粒
UCIe DFx Architecture UDA	DFx architecture specified for chiplets and SiPs that implement UCIe. 为实现UCIe 的芯粒和SiP 指定的DFx 架构
UCIe DFx Message UDM	Generic term forall UCIe Management Transport packets with Protocol ID set to ‘Test and Debug Protocols’. 将协议ID 设置为“Test and Debug Protocols”的所有UCIe 管理传输数据包的通用术语
UCIe Die	This term is used throughout this specification to denote the logic associated with the UCIe Link on any given chiplet with a UCIe Link connection. It is used as a common noun to denote actions or messages sent or received by an implementation of UCIe. 在本规范中，此术语用于表示与任何具有UCIe 链路连接的给定芯粒上的UCIe 链路相关的逻辑。它用作普通名词，表示UCIe 实现发送或接收的动作或消息

Table 1. Terms and Definitions (Sheet 8 of 8)

Term	Definition
UCIe Flit Mode	Operating Mode in which CRC bytes are inserted and checked by the D2D Adapter. If applicable, Retry is also performed by the D2D Adapter. CRC 字节由D2D 适配器插入和检查的操作模式。如果适用，重试也由D2D 适配器执行
UCIe Link	A UCIe connection between two chiplets. These chiplets are Link partners in the context of UCIe since they communicate with each other using a common UCIe Link. 两个芯粒之间的UCIe 连接。在UCIe 的上下文中，这些芯粒是链路伙伴，因为它们使用共同的UCIe 链路相互通信
UCIe Mainband Management Port UCIe 主带管理端口	Chiplet port that implements the Management Link Encapsulation Mechanism and can transfer UCIe Management Transport packets across a point-to-point UCIe mainband link. 实现管理链路封装机制并且能够跨点对点UCIe 主带链路传输UCIe 管理传输数据包的芯粒端口
UCIe Management Transport Protocol UCIeManagement Transport 协议	Protocol used to transfer UCIe Management Transport packets between management entities. 用于在管理实体之间传输UCIe 管理传输数据包的协议
UCIe Raw Format	Operating format in which all the bytes of a Flit are populated by the Protocol Layer. 操作格式，其中Flit 的所有字节均由协议层填充
UCIe Sideband Management Port UCIe 边带管理端口	Chiplet port that implements the Management Link Encapsulation Mechanism and can transfer UCIe Management Transport packets across a point-to-point UCIe sideband link. 实现管理链路封装机制并且能够通过点对点UCIe 边带链路传输UCIe管理传输数据包的芯粒端口
UCLS	UCIe Link Structure UCIe 链路结构
UEDT	UCIe Early Discovery Table UCIe 早期发现表
UHM	UCIe Link Health Monitor UCIe 链路健康监控
UIE	Uncorrectable Internal Error 不可纠正的内部错误
UiRB	UCIe Register BlockUCIe 寄存器块

Term	Definition
UiSRB	UCIe Structure Register Block UCIe 结构寄存器块
UMAP	UCIe Memory Access Protocol UCIe 内存访问协议
Unit Interval UI	Given a data stream of a repeating pattern of alternating 1 and 0 values, the Unit Interval is the value measured by averaging the time interval between voltage transitions, over a time interval sufficiently long to make all intentional frequency modulation of the source clock negligible. 给定一个交替为1 和0 值的重复模式的数据流，单位间隔是通过在足够长的时间间隔内对电压转换之间的时间间隔取平均值来测量的值，以使源时钟的所有有意频率调制可忽略不计
UP	Upstream Port 上游端口
UR	Unsupported Request 不支持的请求
USP	Upstream Switch Port 上游交换端口
VH	Virtual Hierarchy (as defined in CXL Specification)虚拟层级（如CXL 规范中所定义）
vLSM	Virtual Link State Machine 虚拟链路状态机
Vref	Reference voltage for receivers 接收器的参考电压
VTF	Voltage Transfer Function 电压传输函数
WAC	Write Access Control 写入访问控制
zero	Numerical value of 0 in a bit, field, or register, of appropriate width for that bit, field, or register. 在适当宽度的位、字段或寄存器中，位、字段或寄存器的数值为0

Table 2. Unit of Measure Symbols

Symbol	Unit of Measure
b	bit
B	byte
dB	decibel
fF	femtofarad
GB/s	gigabytes per second
GHz	gigahertz
GT/s	gigatransfers per second
KB/s	kilobytes per second
MB/s	megabytes per second
MHz	megahertz
mm	millimeter
ms	millisecond
MT/s	megatransfers per second
mUI	milli-Unit interval
mV	millivolt
mVpp	millivolt peak-to-peak
um	micrometer
us	microsecond
ns	nanosecond
pJ	picojoule
pk	peak
ppm	parts per million
ps	picosecond
s	second
TB/s	terabytes per second
V	volt