本文深入探讨了时序逻辑电路的设计与验证过程，包括寄存器到寄存器构造时间的最大估算、设置时间和保持时间检查，以及在不同时钟域变化下的设置/保持时间检查。文章还讨论了多时钟域检查的挑战，并提到了实验部分涉及Vivado与PYNQ的对比，以及针对softmax函数IP设计和FPGA仿真的详细设计。
17. Register 2 Register Construction Time
Max estimation
Computation
remark
There are still other latency exists.
18. Setup Time and Holding Time Check
18.1. Input to FIFO path
18.2. fifo 2 output
Tsetup = 0,
"5.10" should be minus from the data required time.
18.3. Input 2 output
18.4. Hold time check
Check on the same clock edge
Hold check is irrelative to clock period
The edge of clock for capture and launch paths are the SAME.
Summary
Hold time: actural arrival time - required arrival time > 0
19. Setup/Hold Time Check on Fast and Slow Clock Domain Changes
19.1. Slow 2 Fast domain
Common based period
Setup time should be less than 5 ns (as shown above).
Above figure shows hold check and setup check point respectively.
Set hold time ahead 3 clock cycles, to avoid violation.
19.2. Fast 2 Slow domain
Setup time check from the 4th rising edge of the fast domain.
Hold time check from the 1st rising edge of the fast domain.
20. Multiple Clock Domain Check
20.1. Division
20.2. Non-integer
20.3. Phase shift
Challenging to setup time check, friendly to hold time check.
20.4. False path
False path will be excluded in the static time analysis.
Suggestions:
Minimum False setting: only when necessary
Real intent should not be set false.
21. Experiment
21.1. Vivado vs. PYNQ
21.2. Aim: softmax function IP design and FPGA simulation
21.3. Design
21.4. State of the Art
21.5. Detailed Design
Pre-process
Hardware Design
Division
pipeline
Result Display
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