FPGA Adders: Performance Evaluation and Optimal Design

最新推荐文章于 2026-06-24 01:55:22 发布

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本文探讨了进位跳加法器、进位选择加法器及链式进位加法器等多种加法器的设计与实现。通过Xilinx时序仿真软件评估运行时间，并以配置逻辑块数量衡量成本。结果显示，非优化的进位跳加法器性能并未超越链式进位加法器，成本略有增加。而S-R-R加法器的成本比其他两种降低了约50%，速度提升了7%到36%。

进位跳加法器（Carry-Skip Adder）

进位选择加法器（Carry-Select Adder）

carry lookahead adder 超前进位加法器

链式进位加法器（Ripple-Carry Adder）

对速度和时延的判断方法：

obtain operational times from Xilinx timing-
simulation software

we easure
cost as the number of configurable logic
blocks (CLBs) used.

The performance-to-cost
ratio is cost divided by operational time.

比较了三种加法器：

implemented carrycomplete
and carry-look-ahead adders. By
comparison with the ripple adder, their high
costs, complexities, and high fan-in and fanout
requirements3,4 make them unsuitable
for implementation on FPGA devices.

The carry-ripple adder is a basic building
block of other adders. The timing models we
use in our optimization analyses of carry-skip
and carry-select adders are functions of the
carry-ripple adder’s worst-case operational
time.

Our results show that the nonoptimized
carry-skip adder performs no better than the carryripple
adder, with a small increase in cost.

The S-R-R adder is the most economical to implement, at a
cost about 50% less than the other two adders. The speed
improvement of the S-R-R adder over the carry-ripple adder
is 7% to 36%.

The three configurations are the select-rippleripple
(S-R-R), select-skip-ripple (S-S-R), and select-skip-skip
(S-S-S) adders.