各种加法器的比对分析与Verilog实现（3）

       上一篇博客介绍了Kogge-Stone加法器和brent-kung加法器，本文将用Verilog代码进行实现。原理部分请看：

各种加法器的比对分析与Verilog实现（2）_Albert_yeager的博客

1. Kogge-Stone加法器的Verilog实现

module koggle_stone (
input  [3:0] a_i,b_i,
input  c_i,
output wire [3:0] c_o
);
wire [3:0] q,p;
wire [4:0] carry;

assign p = a_i & b_i;
assign q = a_i | b_i;
assign carry[0] = c_i;
assign carry[1] = p[0] + q[0] & carry[0]; 
assign carry[2] = p[1] + q[1] & p[0] + q[1] & q[0] & carry[0]; 
assign carry[3] = p[2] + q[2] & p[1] + q[2] & q[1] & carry[1]; 
assign carry[4] = p[3] + q[3] & p[2] + q[3] & q[2] & carry[2]; 

assign c_o[3:0] = a_i ^ b_i ^ carry[3:0];
assign c_o[4] = carry[4];
endmodule