【HDLBits习题详解 3】Verification: Reading Simulation（2）Building a circuit from a simulation waveform

1. Sim/circuit1（Combinational circuit 1）

module top_module (
    output 	q,
    input 	a,
    input 	b
);
    assign q = a & b;
endmodule

2. Sim/circuit2（Combinational circuit 2）

方法1：最小项

module top_module (
    output 	q,
    input 	a,
    input 	b,
    input 	c,
    input 	d
);
    assign q = 	(~a)&(~b)&(~c)&(~d)	| 	(~a)&(~b)&c&d	|
        		(~a)&b&(~c)&d 		|	(~a)&b&c&(~d) 	|
    			a&(~b)&(~c)&d 		| 	a&(~b)&c&(~d)	|
        		a&b&(~c)&(~d)		|	a&b&c&d			;
endmodule

方法2：case语句

module top_module (
    output 	reg	q,
    input 		a,
    input 		b,
    input 		c,
    input 		d
);
    always @(*) begin
        q = 0;
        
        case ({a,b,c,d})
            4'b0000: q = 1;
            4'b0011: q = 1;
            4'b0101: q = 1;
            4'b0110: q = 1;
            4'b1001: q = 1;
            4'b1010: q = 1;
            4'b1100: q = 1;
            4'b1111: q = 1;
        endcase
    end
endmodule

方法3：同或

module top_module (
    output 	q,
    input 	a,
    input 	b,
    input 	c,
    input 	d
);
    assign q = a ^~ b ^~ c ^~ d;
endmodule

3. Sim/circuit3（Combinational circuit 3）

module top_module (
    output 	q,
    input 	a,
    input 	b,
    input 	c,
    input 	d
);
    assign q = (a|b) & (c|d);
endmodule

4. Sim/circuit4（Combinational circuit 4）

module top_module (
    output 	q,
    input 	a,
    input 	b,
    input 	c,
    input 	d
);
    assign q = b | c;
endmodule

5. Sim/circuit5（Combinational circuit 5）

module top_module (
    output 	reg	[3:0] q,
    input 		[3:0] a,
    input 		[3:0] b,
    input 		[3:0] c,
    input 		[3:0] d,
    input 		[3:0] e
);
    always @(*) begin
        case (c)
            4'h0:		q = b;
            4'h1:		q = e;
            4'h2:		q = a;
            4'h3:		q = d;
            default:	q = '1;
        endcase
    end
endmodule

6. Sim/circuit6（Combinational circuit 6）

module top_module (
    output 	reg	[15:0] 	q,
    input 		[2:0] 	a
); 
    always @(*) begin
        case (a)
            3'd0: q = 16'h1232;
            3'd1: q = 16'haee0;
            3'd2: q = 16'h27d4;
            3'd3: q = 16'h5a0e;
            3'd4: q = 16'h2066;
            3'd5: q = 16'h64ce;
            3'd6: q = 16'hc526;
            3'd7: q = 16'h2f19;
        endcase
    end
endmodule

7. Sim/circuit7（Sequential circuit 7）

module top_module (
    output 	q ,
    input 	clk,
    input 	a
);
    always @(posedge clk) begin
        q <= ~a;
    end
endmodule

8. Sim/circuit8（Sequential circuit 8）

module top_module (
    output 	p,
    output 	reg	q,
    input 	clock,
    input 	a
);
    // 输出值p
    assign p = (clock) ? a : p;
    
    // 输出值q
    always @(negedge clock) begin
        q <= p;
    end
endmodule

9. Sim/circuit9（Sequential circuit 9）

module top_module (
    output 	[3:0] 	q,
    input 			clk,
    input 			a
);
    always @(posedge clk) begin
        if (a == 1'b1) begin
            q <= 4'd4;
        end else if (q == 4'd6) begin
            q <= 4'd0;
        end else begin
            q <= q + 1'b1;
        end
    end
endmodule

10. Sim/circuit10（Sequential circuit 10）

module top_module (
    output 	reg	q,
    output 	reg	state,
    input 		clk,
    input 		a,
    input 		b
);
    // 输出值q
    always @(*) begin
        q <= (state) ? ~(a^b) : a^b;
    end
    
    // 输出值state
    always @(posedge clk) begin
        if (a^~b == 1'b1) begin
            state <= a & b;
        end else begin
            state <= state;
        end
    end
endmodule