ADS1278学习总结

最新推荐文章于 2025-08-10 16:19:38 发布

原创最新推荐文章于 2025-08-10 16:19:38 发布 · 2.7k 阅读

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这篇博客详细介绍了ADS1278在High-Speed模式下的操作，包括SPI/Frame-Sync数据输出格式、TDM模式的固定和动态数据位置，以及菊花链配置。文章还提到了模数转换启动序列和电源管理注意事项，以及在电路设计中的一些关键要点，如AGND和DGND的连接，数字输入脚的电阻处理，模拟和数字信号的隔离，以及模拟信号参考端的电容配置。

操作模式

MODE[1：0]	Mode Selection	OSR （fmod/fData）	MAX fData
00	High-Speed	64	144531
01	High-Resolution	128	52734
10	Low-Power	64	52734
11	Low-Speed	64	10547

MODE[1：0]	Mode Selection	MAX fCLK(MHz)	CLKDIV	fCLK/fData	DATA RATE (SPS)
00	High-Speed	37	1	256	144531
01	High-Resolution	27	1	512	52734
10	Low-Power	27	1	512	52734
10	Low-Power	13.5	0	256	52734
11	Low-Speed	27	1	2560	10547
11	Low-Speed	5.4(5分频)	0	512	10547

NOTE: The SPI format is limited to a CLK input frequency of 27MHz, maximum. For CLK input operation above 27MHz (High-Speed mode only), use Frame-Sync format.

fCLK(MHz)	VREF(V)	DVDD	Interface
0.1<= fCLK<=27	0.5 to 3.1	1.65 to 1.95	Frams-Sync or SPI
27<= fCLK<=32.768	0.5 to 2.6	1.65 to 1.95	Frams-Sync
32.768<= fCLK<=37	0.5 to 2.1	2.0 to 2.2	Frams-Sync

在High-Speed 模式下，若为TDM方式输出，因为8个Channel均通过OUT1输出且数据

为24bits，故必须保证 SCLK=clk

Data Output Format

FORMAT[2：0]	INTERFACE Protocol	DOUT Mode	Data Position
000	SPI	TDM	Dynamic
001	SPI	TDM	Fixed
010	SPI	Discrete	-
011	Frame-Sync	TDM	Dynamic
100	Frame-Sync	TDM	Fixed
101	Frame-Sync	Discrete	-
110	Modulator Mode	-	-

SPI/Frame-Sync：用相同的串行协议，使用相同的Pin

SCLK， DRDYn/FSYNC，DOUT[4:1]（DOUT[8:1]），and DIN

The serial clock (SCLK) features a Schmitt-triggered input and shifts out data on DOUT on the falling edge. It also shifts in data on the falling edge on DIN when this pin is being used for daisy-chaining. The device shifts data out on the falling edge and the user normally shifts this data in on the rising edge

TDM mode(TDM Mode, Fixed-Position Data)：

the data position of the channels remain fixed, regardless of whether the channels are powered down. If a channel is powered down, the data are forced to zero but occupy the same position within the data stream.

TDM Mode, Dynamic Position Data：

when a channel is powered down, the data from higher channels shift one position in the data stream to fill the vacated data slot. Figure 79 shows the data stream with channel 1 and channel 3 powered down

the channel data are shifted out in parallel using individual channel data output pins DOUT[4:1]/[8:1]. After the 24th SCLK, the channel data are forced to zero. The data are also forced to zero for powered down channels

Daisy Chaining

MODE[1：0]	Mode Selection	CLKDIV	Max Number of Channels
00	High-Speed	1	10
01	High-Resolution	1	21
10	Low-Power	1	21
10	Low-Power	0	10
11	Low-Speed	1	106
11	Low-Speed	0	21

Modulator Output clock Frequencies

(Format=110)

MODE[1：0]	Mode Selection	CLKDIV	MODULATOR Clock Ouput (SCLK)
00	High-Speed	1	fCLK/4
01	High-Resolution	1	fCLK/4
10	Low-Power	1	fCLK/8
10	Low-Power	0	fCLK/4
11	Low-Speed	1	fCLK/40
11	Low-Speed	0	fCLK/8

Star-Up Sequence

. At power-on, bring up the DVDD supply first, followed by IOVDD and then AVDD. Check the first, followed by IOVDD and then AVDD. Check the power-supply sequence for proper order, including the ramp rate of each supply. DVDD and IOVDD may be sequenced at the same time (for example, if the supplies are tied together). Each supply has an internal reset circuit whose outputs are summed together to generate a global power-on reset. After the supplies have exceeded the reset thresholds, 2^18 fCLK cycles are counted before the converter initiates the conversion process. Following the CLK cycles the data for 129 conversions are suppressed by the ADS1274/78 to allow output of fully-settled data.